diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2017-06-05 14:54:46 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-06-14 15:00:13 -0700 |
| commit | fb7d32e5881ef2445e8fe2305005f5590d4a7cfa (patch) | |
| tree | 24c77f58069dddfc1e8c530d06f9bf94bc77f613 /plat/arm | |
| parent | 6311f63de02ee04d93016242977ade4727089de8 (diff) | |
Unique names for defines in the CPU libraries
This patch makes all the defines in the CPU libraries unique,
by prefixing them with the CPU name.
NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE
TO START USING THE UPDATED NAMES
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/arm')
| -rw-r--r-- | plat/arm/board/juno/aarch64/juno_helpers.S | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/plat/arm/board/juno/aarch64/juno_helpers.S b/plat/arm/board/juno/aarch64/juno_helpers.S index e4113602..8d00a1a7 100644 --- a/plat/arm/board/juno/aarch64/juno_helpers.S +++ b/plat/arm/board/juno/aarch64/juno_helpers.S @@ -86,9 +86,9 @@ func JUNO_HANDLER(0) * Cortex-A57 specific settings * -------------------------------------------------------------------- */ - mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ - (L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) - msr L2CTLR_EL1, x0 + mov x0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ + (CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT)) + msr CORTEX_A57_L2CTLR_EL1, x0 1: isb ret @@ -123,8 +123,8 @@ A57: * Cortex-A57 specific settings * -------------------------------------------------------------------- */ - mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) - msr L2CTLR_EL1, x0 + mov x0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) + msr CORTEX_A57_L2CTLR_EL1, x0 isb ret endfunc JUNO_HANDLER(1) @@ -157,9 +157,9 @@ A72: * Cortex-A72 specific settings * -------------------------------------------------------------------- */ - mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ - (L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) - msr L2CTLR_EL1, x0 + mov x0, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ + (CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES << CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT)) + msr CORTEX_A57_L2CTLR_EL1, x0 isb ret endfunc JUNO_HANDLER(2) |