diff options
| author | davidcunado-arm <david.cunado@arm.com> | 2017-06-16 12:06:24 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-06-16 12:06:24 +0100 |
| commit | 6de8b24f52cf2bd74adefbaa86dd2a0676c3eaa2 (patch) | |
| tree | f7b88c25ab174e201cdc67a35fcb205b94f04363 /plat/arm | |
| parent | 0dc3c353054896722b7cbfbd04a4d845619485e7 (diff) | |
| parent | ab712fd86b4790f171f355508895de198330cfb9 (diff) | |
Merge pull request #953 from vwadekar/tegra-misra-fixes-v1
Tegra misra fixes v1
Diffstat (limited to 'plat/arm')
| -rw-r--r-- | plat/arm/board/juno/aarch64/juno_helpers.S | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/plat/arm/board/juno/aarch64/juno_helpers.S b/plat/arm/board/juno/aarch64/juno_helpers.S index e4113602..8d00a1a7 100644 --- a/plat/arm/board/juno/aarch64/juno_helpers.S +++ b/plat/arm/board/juno/aarch64/juno_helpers.S @@ -86,9 +86,9 @@ func JUNO_HANDLER(0) * Cortex-A57 specific settings * -------------------------------------------------------------------- */ - mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ - (L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) - msr L2CTLR_EL1, x0 + mov x0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ + (CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT)) + msr CORTEX_A57_L2CTLR_EL1, x0 1: isb ret @@ -123,8 +123,8 @@ A57: * Cortex-A57 specific settings * -------------------------------------------------------------------- */ - mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) - msr L2CTLR_EL1, x0 + mov x0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) + msr CORTEX_A57_L2CTLR_EL1, x0 isb ret endfunc JUNO_HANDLER(1) @@ -157,9 +157,9 @@ A72: * Cortex-A72 specific settings * -------------------------------------------------------------------- */ - mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ - (L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) - msr L2CTLR_EL1, x0 + mov x0, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ + (CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES << CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT)) + msr CORTEX_A57_L2CTLR_EL1, x0 isb ret endfunc JUNO_HANDLER(2) |