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| author | Soby Mathew <soby.mathew@arm.com> | 2018-02-20 12:50:47 +0000 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2018-02-22 15:19:03 +0000 |
| commit | caf4eca135f4f0bac48ce297dc66bd86c80ff1bf (patch) | |
| tree | 4331c7118067f84c4e549975bfb9ed38cd52a73e /plat/arm | |
| parent | 81bf6aae6855d3afb6c99ac82a75f576f6af6131 (diff) | |
ARM Platforms: Add CASSERT for BL2_BASE
Change-Id: I93e491fde2a991fc39584c2762f33cbea40541e3
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Diffstat (limited to 'plat/arm')
| -rw-r--r-- | plat/arm/common/arm_bl2_setup.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c index 5d83118a..906ed197 100644 --- a/plat/arm/common/arm_bl2_setup.c +++ b/plat/arm/common/arm_bl2_setup.c @@ -24,6 +24,20 @@ /* Data structure which holds the extents of the trusted SRAM for BL2 */ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); +/* + * Check that BL2_BASE is atleast a page over ARM_BL_RAM_BASE. The page is for + * `meminfo_t` data structure and TB_FW_CONFIG passed from BL1. Not needed + * when BL2 is compiled for BL_AT_EL3 as BL2 doesn't need any info from BL1 and + * BL2 is loaded at base of usable SRAM. + */ +#if BL2_AT_EL3 +#define BL1_MEMINFO_OFFSET 0x0 +#else +#define BL1_MEMINFO_OFFSET PAGE_SIZE +#endif + +CASSERT(BL2_BASE >= (ARM_BL_RAM_BASE + BL1_MEMINFO_OFFSET), assert_bl2_base_overflows); + /* Weak definitions may be overridden in specific ARM standard platform */ #pragma weak bl2_early_platform_setup #pragma weak bl2_platform_setup |