diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2018-10-24 16:38:12 +0100 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2018-11-14 09:50:06 +0000 |
| commit | a561e41bf1d238572b272f4f97b2a21f473a29fa (patch) | |
| tree | df6111399f6c6c3a0c4ee97142fc0fc026fa248b /plat/allwinner | |
| parent | d93eb4467a0ca09d359f242b19f584a58e4e805b (diff) | |
allwinner: power: add enable switches for DCDC1/5
The DCDC1 and DCDC5 power rails didn't specify the enable bits. This
isn't critical, since those rails are on by default (and are needed for
every board), but it is inconsistent.
Add the respective enable bits for those two rails.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'plat/allwinner')
| -rw-r--r-- | plat/allwinner/sun50i_a64/sunxi_power.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index 8db248b4..bc796c5d 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -181,8 +181,8 @@ struct axp_regulator { unsigned char switch_reg; unsigned char switch_bit; } regulators[] = { - {"dcdc1", 1600, 3400, 100, NO_SPLIT, 0x20, 0xff, 9}, - {"dcdc5", 800, 1840, 10, 32, 0x24, 0xff, 9}, + {"dcdc1", 1600, 3400, 100, NO_SPLIT, 0x20, 0x10, 0}, + {"dcdc5", 800, 1840, 10, 32, 0x24, 0x10, 4}, {"dldo1", 700, 3300, 100, NO_SPLIT, 0x15, 0x12, 3}, {"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4}, {"dldo3", 700, 3300, 100, NO_SPLIT, 0x17, 0x12, 5}, |