diff options
| author | Andrew F. Davis <afd@ti.com> | 2019-04-25 14:33:30 -0400 |
|---|---|---|
| committer | John Tsichritzis <john.tsichritzis@arm.com> | 2019-06-06 11:20:26 +0100 |
| commit | 48d6b2643462b43ed617ca3751121a5587881e44 (patch) | |
| tree | 351d6dc998168666a4d8211372834e523e7d7f26 /lib | |
| parent | 65f7b81728d0701e93bd13cee4e88375ec9e9b17 (diff) | |
ti: k3: common: Remove coherency workaround for AM65x
We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the last accessed areas all being marked as non-cached by
USE_COHERENT_MEM we can rely on that to workaround our interconnect
issues. Remove the old workaround.
Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7
Signed-off-by: Andrew F. Davis <afd@ti.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a53.S | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index 6fd3c53f..b105de26 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -279,13 +279,11 @@ endfunc cortex_a53_reset_func func cortex_a53_core_pwr_dwn mov x18, x30 -#if !TI_AM65X_WORKAROUND /* --------------------------------------------- * Turn off caches. * --------------------------------------------- */ bl cortex_a53_disable_dcache -#endif /* --------------------------------------------- * Flush L1 caches. @@ -305,13 +303,11 @@ endfunc cortex_a53_core_pwr_dwn func cortex_a53_cluster_pwr_dwn mov x18, x30 -#if !TI_AM65X_WORKAROUND /* --------------------------------------------- * Turn off caches. * --------------------------------------------- */ bl cortex_a53_disable_dcache -#endif /* --------------------------------------------- * Flush L1 caches. |