diff options
| author | Alexei Fedorov <Alexei.Fedorov@arm.com> | 2019-08-20 15:22:44 +0100 |
|---|---|---|
| committer | Paul Beesley <paul.beesley@arm.com> | 2019-09-26 15:36:02 +0000 |
| commit | c3e8b0be9bde36d220beea5d0452ecd04dcd94c6 (patch) | |
| tree | 2f5efa0f2fc2f922e19abd9e1eadebc0c8eb8f85 /lib | |
| parent | 69ef7b7ffe66b64bdffee0a387774e7088022503 (diff) | |
AArch32: Disable Secure Cycle Counter
This patch changes implementation for disabling Secure Cycle
Counter. For ARMv8.5 the counter gets disabled by setting
SDCR.SCCD bit on CPU cold/warm boot. For the earlier
architectures PMCR register is saved/restored on secure
world entry/exit from/to Non-secure state, and cycle counting
gets disabled by setting PMCR.DP bit.
In 'include\aarch32\arch.h' header file new
ARMv8.5-PMU related definitions were added.
Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/el3_runtime/aarch32/context_mgmt.c | 26 |
1 files changed, 22 insertions, 4 deletions
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c index a4702fcc..73d1e354 100644 --- a/lib/el3_runtime/aarch32/context_mgmt.c +++ b/lib/el3_runtime/aarch32/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -281,10 +281,28 @@ void cm_prepare_el3_exit(uint32_t security_state) * * HDCR.HPMN: Set to value of PMCR.N which is the * architecturally-defined reset value. + * + * HDCR.HLP: Set to one so that event counter + * overflow, that is recorded in PMOVSCLR[0-30], + * occurs on the increment that changes + * PMEVCNTR<n>[63] from 1 to 0, when ARMv8.5-PMU is + * implemented. This bit is RES0 in versions of the + * architecture earlier than ARMv8.5, setting it to 1 + * doesn't have any effect on them. + * This bit is Reserved, UNK/SBZP in ARMv7. + * + * HDCR.HPME: Set to zero to disable EL2 Event + * counters. */ - write_hdcr(HDCR_RESET_VAL | - ((read_pmcr() & PMCR_N_BITS) >> PMCR_N_SHIFT)); - +#if (ARM_ARCH_MAJOR > 7) + write_hdcr((HDCR_RESET_VAL | HDCR_HLP_BIT | + ((read_pmcr() & PMCR_N_BITS) >> + PMCR_N_SHIFT)) & ~HDCR_HPME_BIT); +#else + write_hdcr((HDCR_RESET_VAL | + ((read_pmcr() & PMCR_N_BITS) >> + PMCR_N_SHIFT)) & ~HDCR_HPME_BIT); +#endif /* * Set HSTR to its architectural reset value so that * access to system registers in the cproc=1111 |