diff options
| author | Summer Qin <summer.qin@arm.com> | 2017-03-16 17:16:34 +0000 |
|---|---|---|
| committer | Summer Qin <summer.qin@arm.com> | 2017-03-28 10:32:17 +0100 |
| commit | 5d21b037e16ab8f7c5e63db84a6a9148b7a44a14 (patch) | |
| tree | eb7140f2cb1c602ee3d3dae70946d9e3ee82655c /lib/xlat_tables_v2 | |
| parent | 891685a51146c50234bd5ce49d29cb0fd9f290c8 (diff) | |
Add support to change xlat_tables to non-cacheable
This patch adds an additional flag `XLAT_TABLE_NC` which marks the
translation tables as Non-cacheable for MMU accesses.
Change-Id: I7c28ab87f0ce67da237fadc3627beb6792860fd4
Signed-off-by: Summer Qin <summer.qin@arm.com>
Diffstat (limited to 'lib/xlat_tables_v2')
| -rw-r--r-- | lib/xlat_tables_v2/aarch32/xlat_tables_arch.c | 20 | ||||
| -rw-r--r-- | lib/xlat_tables_v2/aarch64/xlat_tables_arch.c | 15 |
2 files changed, 25 insertions, 10 deletions
diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c index 7de90304..ba0e53d6 100644 --- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c @@ -122,13 +122,21 @@ void enable_mmu_internal_secure(unsigned int flags, uint64_t *base_table) write_mair0(mair0); /* - * Set TTBCR bits as well. Set TTBR0 table properties as Inner - * & outer WBWA & shareable. Disable TTBR1. + * Set TTBCR bits as well. Set TTBR0 table properties. Disable TTBR1. */ - ttbcr = TTBCR_EAE_BIT | - TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | - TTBCR_RGN0_INNER_WBA | - (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE)); + if (flags & XLAT_TABLE_NC) { + /* Inner & outer non-cacheable non-shareable. */ + ttbcr = TTBCR_EAE_BIT | + TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | + TTBCR_RGN0_INNER_NC | + (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE)); + } else { + /* Inner & outer WBWA & shareable. */ + ttbcr = TTBCR_EAE_BIT | + TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | + TTBCR_RGN0_INNER_WBA | + (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE)); + } ttbcr |= TTBCR_EPD1_BIT; write_ttbcr(ttbcr); diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c index 235fa445..575ac71c 100644 --- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c @@ -201,11 +201,18 @@ void init_xlat_tables_arch(unsigned long long max_pa) write_mair_el##_el(mair); \ \ /* Set TCR bits as well. */ \ - /* Inner & outer WBWA & shareable. */ \ /* Set T0SZ to (64 - width of virtual address space) */ \ - tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \ - TCR_RGN_INNER_WBA | \ - (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\ + if (flags & XLAT_TABLE_NC) { \ + /* Inner & outer non-cacheable non-shareable. */\ + tcr = TCR_SH_NON_SHAREABLE | \ + TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC | \ + (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\ + } else { \ + /* Inner & outer WBWA & shareable. */ \ + tcr = TCR_SH_INNER_SHAREABLE | \ + TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | \ + (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\ + } \ tcr |= _tcr_extra; \ write_tcr_el##_el(tcr); \ \ |