diff options
| author | danh-arm <dan.handley@arm.com> | 2016-12-20 12:27:58 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-12-20 12:27:58 +0000 |
| commit | 67748e4827976f3b13f8bc1281b3c4b59da87e4a (patch) | |
| tree | 1d1c8fcb43ebe67ba45cc334fd0ea6e58f09e335 /lib/psci | |
| parent | 9acdafbccf730179406ce7693772d7f7dcc4ae3c (diff) | |
| parent | 5dd9dbb5bfe64b1eb2e78648f3a2e900678ef433 (diff) | |
Merge pull request #788 from jeenu-arm/cpuops-framework
Add provision to extend CPU operations at more levels
Diffstat (limited to 'lib/psci')
| -rw-r--r-- | lib/psci/aarch32/psci_helpers.S | 19 | ||||
| -rw-r--r-- | lib/psci/aarch64/psci_helpers.S | 20 |
2 files changed, 8 insertions, 31 deletions
diff --git a/lib/psci/aarch32/psci_helpers.S b/lib/psci/aarch32/psci_helpers.S index 5a41ff31..9f991dfe 100644 --- a/lib/psci/aarch32/psci_helpers.S +++ b/lib/psci/aarch32/psci_helpers.S @@ -65,22 +65,13 @@ func psci_do_pwrdown_cache_maintenance bl do_stack_maintenance /* --------------------------------------------- - * Determine how many levels of cache will be - * subject to cache maintenance. Power level - * 0 implies that only the cpu is being powered - * down. Only the L1 data cache needs to be - * flushed to the PoU in this case. For a higher - * power level we are assuming that a flush - * of L1 data and L2 unified cache is enough. - * This information should be provided by the - * platform. + * Invoke CPU-specifc power down operations for + * the appropriate level * --------------------------------------------- */ - cmp r4, #PSCI_CPU_PWR_LVL - pop {r4,lr} - - beq prepare_core_pwr_dwn - b prepare_cluster_pwr_dwn + mov r0, r4 + pop {r4, lr} + b prepare_cpu_pwr_dwn endfunc psci_do_pwrdown_cache_maintenance diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S index eaa17c72..108f0687 100644 --- a/lib/psci/aarch64/psci_helpers.S +++ b/lib/psci/aarch64/psci_helpers.S @@ -59,24 +59,11 @@ func psci_do_pwrdown_cache_maintenance stp x19, x20, [sp,#-16]! /* --------------------------------------------- - * Determine to how many levels of cache will be - * subject to cache maintenance. Power level - * 0 implies that only the cpu is being powered - * down. Only the L1 data cache needs to be - * flushed to the PoU in this case. For a higher - * power level we are assuming that a flush - * of L1 data and L2 unified cache is enough. - * This information should be provided by the - * platform. + * Invoke CPU-specific power down operations for + * the appropriate level * --------------------------------------------- */ - cmp w0, #PSCI_CPU_PWR_LVL - b.eq do_core_pwr_dwn - bl prepare_cluster_pwr_dwn - b do_stack_maintenance - -do_core_pwr_dwn: - bl prepare_core_pwr_dwn + bl prepare_cpu_pwr_dwn /* --------------------------------------------- * Do stack maintenance by flushing the used @@ -84,7 +71,6 @@ do_core_pwr_dwn: * remainder. * --------------------------------------------- */ -do_stack_maintenance: bl plat_get_my_stack /* --------------------------------------------- |