Fix MISRA defects in extension libs

No functional changes.

Change-Id: I2f28f20944f552447ac4e9e755493cd7c0ea1192
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

5 files changed, 74 insertions, 66 deletions

diff --git a/lib/extensions/amu/aarch32/amu.c b/lib/extensions/amu/aarch32/amu.c
index 05c98f1c..585d908f 100644
--- a/lib/extensions/amu/aarch32/amu.c
+++ b/lib/extensions/amu/aarch32/amu.c
@@ -10,6 +10,7 @@
 #include <arch_helpers.h>
 #include <platform.h>
 #include <pubsub_events.h>
+#include <stdbool.h>
 
 #define AMU_GROUP0_NR_COUNTERS	4
 
@@ -20,17 +21,17 @@ struct amu_ctx {
 
 static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
 
-int amu_supported(void)
+bool amu_supported(void)
 {
 	uint64_t features;
 
 	features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
-	return (features & ID_PFR0_AMU_MASK) == 1;
+	return (features & ID_PFR0_AMU_MASK) == 1U;
 }
 
-void amu_enable(int el2_unused)
+void amu_enable(bool el2_unused)
 {
-	if (amu_supported() == 0)
+	if (!amu_supported())
 		return;
 
 	if (el2_unused) {
@@ -54,8 +55,8 @@ void amu_enable(int el2_unused)
 /* Read the group 0 counter identified by the given `idx`. */
 uint64_t amu_group0_cnt_read(int idx)
 {
-	assert(amu_supported() != 0);
-	assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
+	assert(amu_supported());
+	assert((idx >= 0) && (idx < AMU_GROUP0_NR_COUNTERS));
 
 	return amu_group0_cnt_read_internal(idx);
 }
@@ -63,8 +64,8 @@ uint64_t amu_group0_cnt_read(int idx)
 /* Write the group 0 counter identified by the given `idx` with `val`. */
 void amu_group0_cnt_write(int idx, uint64_t val)
 {
-	assert(amu_supported() != 0);
-	assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
+	assert(amu_supported());
+	assert((idx >= 0) && (idx < AMU_GROUP0_NR_COUNTERS));
 
 	amu_group0_cnt_write_internal(idx, val);
 	isb();
@@ -73,8 +74,8 @@ void amu_group0_cnt_write(int idx, uint64_t val)
 /* Read the group 1 counter identified by the given `idx`. */
 uint64_t amu_group1_cnt_read(int idx)
 {
-	assert(amu_supported() != 0);
-	assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
+	assert(amu_supported());
+	assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
 
 	return amu_group1_cnt_read_internal(idx);
 }
@@ -82,8 +83,8 @@ uint64_t amu_group1_cnt_read(int idx)
 /* Write the group 1 counter identified by the given `idx` with `val`. */
 void amu_group1_cnt_write(int idx, uint64_t val)
 {
-	assert(amu_supported() != 0);
-	assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
+	assert(amu_supported());
+	assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
 
 	amu_group1_cnt_write_internal(idx, val);
 	isb();
@@ -91,8 +92,8 @@ void amu_group1_cnt_write(int idx, uint64_t val)
 
 void amu_group1_set_evtype(int idx, unsigned int val)
 {
-	assert(amu_supported() != 0);
-	assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
+	assert(amu_supported());
+	assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
 
 	amu_group1_set_evtype_internal(idx, val);
 	isb();
@@ -103,7 +104,7 @@ static void *amu_context_save(const void *arg)
 	struct amu_ctx *ctx;
 	int i;
 
-	if (amu_supported() == 0)
+	if (!amu_supported())
 		return (void *)-1;
 
 	ctx = &amu_ctxs[plat_my_core_pos()];
@@ -126,7 +127,7 @@ static void *amu_context_save(const void *arg)
 	for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
 		ctx->group1_cnts[i] = amu_group1_cnt_read(i);
 
-	return 0;
+	return (void *)0;
 }
 
 static void *amu_context_restore(const void *arg)
@@ -134,13 +135,13 @@ static void *amu_context_restore(const void *arg)
 	struct amu_ctx *ctx;
 	int i;
 
-	if (amu_supported() == 0)
+	if (!amu_supported())
 		return (void *)-1;
 
 	ctx = &amu_ctxs[plat_my_core_pos()];
 
 	/* Counters were disabled in `amu_context_save()` */
-	assert(read_amcntenset0() == 0 && read_amcntenset1() == 0);
+	assert((read_amcntenset0() == 0U) && (read_amcntenset1() == 0U));
 
 	/* Restore group 0 counters */
 	for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
@@ -153,7 +154,7 @@ static void *amu_context_restore(const void *arg)
 
 	/* Enable group 1 counters */
 	write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
-	return 0;
+	return (void *)0;
 }
 
 SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, amu_context_save);
diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c
index 5d556e5d..1564e840 100644
--- a/lib/extensions/amu/aarch64/amu.c
+++ b/lib/extensions/amu/aarch64/amu.c
@@ -11,6 +11,7 @@
 #include <assert.h>
 #include <platform.h>
 #include <pubsub_events.h>
+#include <stdbool.h>
 
 #define AMU_GROUP0_NR_COUNTERS	4
 
@@ -21,23 +22,23 @@ struct amu_ctx {
 
 static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
 
-int amu_supported(void)
+bool amu_supported(void)
 {
 	uint64_t features;
 
 	features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT;
-	return (features & ID_AA64PFR0_AMU_MASK) == 1;
+	return (features & ID_AA64PFR0_AMU_MASK) == 1U;
 }
 
 /*
  * Enable counters.  This function is meant to be invoked
  * by the context management library before exiting from EL3.
  */
-void amu_enable(int el2_unused)
+void amu_enable(bool el2_unused)
 {
 	uint64_t v;
 
-	if (amu_supported() == 0)
+	if (!amu_supported())
 		return;
 
 	if (el2_unused) {
@@ -67,8 +68,8 @@ void amu_enable(int el2_unused)
 /* Read the group 0 counter identified by the given `idx`. */
 uint64_t amu_group0_cnt_read(int idx)
 {
-	assert(amu_supported() != 0);
-	assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
+	assert(amu_supported());
+	assert((idx >= 0) && (idx < AMU_GROUP0_NR_COUNTERS));
 
 	return amu_group0_cnt_read_internal(idx);
 }
@@ -76,8 +77,8 @@ uint64_t amu_group0_cnt_read(int idx)
 /* Write the group 0 counter identified by the given `idx` with `val`. */
 void amu_group0_cnt_write(int idx, uint64_t val)
 {
-	assert(amu_supported() != 0);
-	assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
+	assert(amu_supported());
+	assert((idx >= 0) && (idx < AMU_GROUP0_NR_COUNTERS));
 
 	amu_group0_cnt_write_internal(idx, val);
 	isb();
@@ -86,8 +87,8 @@ void amu_group0_cnt_write(int idx, uint64_t val)
 /* Read the group 1 counter identified by the given `idx`. */
 uint64_t amu_group1_cnt_read(int idx)
 {
-	assert(amu_supported() != 0);
-	assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
+	assert(amu_supported());
+	assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
 
 	return amu_group1_cnt_read_internal(idx);
 }
@@ -95,8 +96,8 @@ uint64_t amu_group1_cnt_read(int idx)
 /* Write the group 1 counter identified by the given `idx` with `val`. */
 void amu_group1_cnt_write(int idx, uint64_t val)
 {
-	assert(amu_supported() != 0);
-	assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
+	assert(amu_supported());
+	assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
 
 	amu_group1_cnt_write_internal(idx, val);
 	isb();
@@ -108,8 +109,8 @@ void amu_group1_cnt_write(int idx, uint64_t val)
  */
 void amu_group1_set_evtype(int idx, unsigned int val)
 {
-	assert(amu_supported() != 0);
-	assert (idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
+	assert(amu_supported());
+	assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
 
 	amu_group1_set_evtype_internal(idx, val);
 	isb();
@@ -120,14 +121,14 @@ static void *amu_context_save(const void *arg)
 	struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
 	int i;
 
-	if (amu_supported() == 0)
+	if (!amu_supported())
 		return (void *)-1;
 
 	/* Assert that group 0/1 counter configuration is what we expect */
-	assert(read_amcntenset0_el0() == AMU_GROUP0_COUNTERS_MASK &&
-	       read_amcntenset1_el0() == AMU_GROUP1_COUNTERS_MASK);
+	assert((read_amcntenset0_el0() == AMU_GROUP0_COUNTERS_MASK) &&
+	       (read_amcntenset1_el0() == AMU_GROUP1_COUNTERS_MASK));
 
-	assert((sizeof(int) * 8) - __builtin_clz(AMU_GROUP1_COUNTERS_MASK)
+	assert(((sizeof(int) * 8) - __builtin_clz(AMU_GROUP1_COUNTERS_MASK))
 		<= AMU_GROUP1_NR_COUNTERS);
 
 	/*
@@ -146,7 +147,7 @@ static void *amu_context_save(const void *arg)
 	for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
 		ctx->group1_cnts[i] = amu_group1_cnt_read(i);
 
-	return 0;
+	return (void *)0;
 }
 
 static void *amu_context_restore(const void *arg)
@@ -154,30 +155,30 @@ static void *amu_context_restore(const void *arg)
 	struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
 	int i;
 
-	if (amu_supported() == 0)
+	if (!amu_supported())
 		return (void *)-1;
 
 	/* Counters were disabled in `amu_context_save()` */
-	assert(read_amcntenset0_el0() == 0 && read_amcntenset1_el0() == 0);
+	assert((read_amcntenset0_el0() == 0U) && (read_amcntenset1_el0() == 0U));
 
-	assert((sizeof(int) * 8) - __builtin_clz(AMU_GROUP1_COUNTERS_MASK)
+	assert(((sizeof(int) * 8U) - __builtin_clz(AMU_GROUP1_COUNTERS_MASK))
 		<= AMU_GROUP1_NR_COUNTERS);
 
 	/* Restore group 0 counters */
 	for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
-		if (AMU_GROUP0_COUNTERS_MASK & (1U << i))
+		if ((AMU_GROUP0_COUNTERS_MASK & (1U << i)) != 0U)
 			amu_group0_cnt_write(i, ctx->group0_cnts[i]);
 
 	/* Restore group 1 counters */
 	for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
-		if (AMU_GROUP1_COUNTERS_MASK & (1U << i))
+		if ((AMU_GROUP1_COUNTERS_MASK & (1U << i)) != 0U)
 			amu_group1_cnt_write(i, ctx->group1_cnts[i]);
 
 	/* Restore group 0/1 counter configuration */
 	write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK);
 	write_amcntenset1_el0(AMU_GROUP1_COUNTERS_MASK);
 
-	return 0;
+	return (void *)0;
 }
 
 SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, amu_context_save);
diff --git a/lib/extensions/mpam/mpam.c b/lib/extensions/mpam/mpam.c
index e628827b..d57bb470 100644
--- a/lib/extensions/mpam/mpam.c
+++ b/lib/extensions/mpam/mpam.c
@@ -16,7 +16,7 @@ bool mpam_supported(void)
 	return ((features & ID_AA64PFR0_MPAM_MASK) != 0U);
 }
 
-void mpam_enable(int el2_unused)
+void mpam_enable(bool el2_unused)
 {
 	if (!mpam_supported())
 		return;
@@ -31,7 +31,7 @@ void mpam_enable(int el2_unused)
 	 * If EL2 is implemented but unused, disable trapping to EL2 when lower
 	 * ELs access their own MPAM registers.
 	 */
-	if (el2_unused != 0) {
+	if (el2_unused) {
 		write_mpam2_el2(0);
 
 		if ((read_mpamidr_el1() & MPAMIDR_HAS_HCR_BIT) != 0U)
diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index dc358403..e5df015b 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c
@@ -8,26 +8,30 @@
 #include <arch_helpers.h>
 #include <pubsub.h>
 #include <spe.h>
+#include <stdbool.h>
 
-/*
- * The assembler does not yet understand the psb csync mnemonic
- * so use the equivalent hint instruction.
- */
-#define psb_csync()	asm volatile("hint #17")
+static inline void psb_csync(void)
+{
+	/*
+	 * The assembler does not yet understand the psb csync mnemonic
+	 * so use the equivalent hint instruction.
+	 */
+	__asm__ volatile("hint #17");
+}
 
-int spe_supported(void)
+bool spe_supported(void)
 {
 	uint64_t features;
 
 	features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
-	return (features & ID_AA64DFR0_PMS_MASK) == 1;
+	return (features & ID_AA64DFR0_PMS_MASK) == 1U;
 }
 
-void spe_enable(int el2_unused)
+void spe_enable(bool el2_unused)
 {
 	uint64_t v;
 
-	if (spe_supported() == 0)
+	if (!spe_supported())
 		return;
 
 	if (el2_unused) {
@@ -59,7 +63,7 @@ void spe_disable(void)
 {
 	uint64_t v;
 
-	if (spe_supported() == 0)
+	if (!spe_supported())
 		return;
 
 	/* Drain buffered data */
@@ -75,13 +79,14 @@ void spe_disable(void)
 
 static void *spe_drain_buffers_hook(const void *arg)
 {
-	if (spe_supported() == 0)
+	if (!spe_supported())
 		return (void *)-1;
 
 	/* Drain buffered data */
 	psb_csync();
 	dsbnsh();
-	return 0;
+
+	return (void *)0;
 }
 
 SUBSCRIBE_TO_EVENT(cm_entering_secure_world, spe_drain_buffers_hook);
diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c
index 64424878..e031bf61 100644
--- a/lib/extensions/sve/sve.c
+++ b/lib/extensions/sve/sve.c
@@ -7,21 +7,22 @@
 #include <arch.h>
 #include <arch_helpers.h>
 #include <pubsub.h>
+#include <stdbool.h>
 #include <sve.h>
 
-int sve_supported(void)
+bool sve_supported(void)
 {
 	uint64_t features;
 
 	features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
-	return (features & ID_AA64PFR0_SVE_MASK) == 1;
+	return (features & ID_AA64PFR0_SVE_MASK) == 1U;
 }
 
 static void *disable_sve_hook(const void *arg)
 {
 	uint64_t cptr;
 
-	if (sve_supported() == 0)
+	if (!sve_supported())
 		return (void *)-1;
 
 	/*
@@ -39,14 +40,14 @@ static void *disable_sve_hook(const void *arg)
 	 * No explicit ISB required here as ERET to switch to Secure
 	 * world covers it
 	 */
-	return 0;
+	return (void *)0;
 }
 
 static void *enable_sve_hook(const void *arg)
 {
 	uint64_t cptr;
 
-	if (sve_supported() == 0)
+	if (!sve_supported())
 		return (void *)-1;
 
 	/*
@@ -60,14 +61,14 @@ static void *enable_sve_hook(const void *arg)
 	 * No explicit ISB required here as ERET to switch to Non-secure
 	 * world covers it
 	 */
-	return 0;
+	return (void *)0;
 }
 
-void sve_enable(int el2_unused)
+void sve_enable(bool el2_unused)
 {
 	uint64_t cptr;
 
-	if (sve_supported() == 0)
+	if (!sve_supported())
 		return;
 
 #if CTX_INCLUDE_FPREGS