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| author | Antonio Niño Díaz <antonio.ninodiaz@arm.com> | 2019-02-28 10:19:24 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-28 10:19:24 +0000 |
| commit | 64503b2f81bbd12051d8e0fd065a5a0b0c38bd2a (patch) | |
| tree | 89a0e3acb4e84aabc69b66f8f5f9e16dd9358a81 /lib/el3_runtime | |
| parent | 1baa28bb2dc79f23c550d67604324afd222221c3 (diff) | |
| parent | 5c6aa01affe14c40efdebdc9450cdbc4ae0bc494 (diff) | |
Merge pull request #1839 from loumay-arm/lm/a7x_errata
Cortex-A73/75/76 errata workaround
Diffstat (limited to 'lib/el3_runtime')
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 83f6e489..89d7ed68 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -187,6 +187,14 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; } +#if ERRATA_A75_764081 + /* + * If workaround of errata 764081 for Cortex-A75 is used then set + * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. + */ + sctlr_elx |= SCTLR_IESB_BIT; +#endif + /* * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 * and other EL2 registers are set up by cm_prepare_ns_entry() as they @@ -319,6 +327,14 @@ void cm_prepare_el3_exit(uint32_t security_state) CTX_SCTLR_EL1); sctlr_elx &= SCTLR_EE_BIT; sctlr_elx |= SCTLR_EL2_RES1; +#if ERRATA_A75_764081 + /* + * If workaround of errata 764081 for Cortex-A75 is used + * then set SCTLR_EL2.IESB to enable Implicit Error + * Synchronization Barrier. + */ + sctlr_elx |= SCTLR_IESB_BIT; +#endif write_sctlr_el2(sctlr_elx); } else if (el_implemented(2) != EL_IMPL_NONE) { el2_unused = true; |