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authorBalint Dobszay <balint.dobszay@arm.com>2019-07-03 13:02:56 +0200
committerBalint Dobszay <balint.dobszay@arm.com>2019-07-10 12:14:20 +0200
commitf363deb6d409e64de70d25af868a91edb94c186c (patch)
tree1099d4b421ef3ed44a7e8ec87df7948b0701f0a5 /lib/cpus
parent21bde92ff6d20ef2d3a2651fd729a1579232313b (diff)
Rename Cortex-Deimos to Cortex-A77
Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Diffstat (limited to 'lib/cpus')
-rw-r--r--lib/cpus/aarch64/cortex_a77.S (renamed from lib/cpus/aarch64/cortex_deimos.S)40
1 files changed, 20 insertions, 20 deletions
diff --git a/lib/cpus/aarch64/cortex_deimos.S b/lib/cpus/aarch64/cortex_a77.S
index df4c1285..f3fd5e19 100644
--- a/lib/cpus/aarch64/cortex_deimos.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -7,48 +7,48 @@
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
-#include <cortex_deimos.h>
+#include <cortex_a77.h>
#include <cpu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
-#error "Deimos must be compiled with HW_ASSISTED_COHERENCY enabled"
+#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex-Deimos supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
-func cortex_deimos_core_pwr_dwn
+func cortex_a77_core_pwr_dwn
/* ---------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, CORTEX_DEIMOS_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_DEIMOS_CPUPWRCTLR_EL1, x0
+ mrs x0, CORTEX_A77_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_A77_CPUPWRCTLR_EL1, x0
isb
ret
-endfunc cortex_deimos_core_pwr_dwn
+endfunc cortex_a77_core_pwr_dwn
#if REPORT_ERRATA
/*
- * Errata printing function for Cortex Deimos. Must follow AAPCS.
+ * Errata printing function for Cortex-A77. Must follow AAPCS.
*/
-func cortex_deimos_errata_report
+func cortex_a77_errata_report
ret
-endfunc cortex_deimos_errata_report
+endfunc cortex_a77_errata_report
#endif
/* ---------------------------------------------
- * This function provides Cortex-Deimos specific
+ * This function provides Cortex-A77 specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
@@ -56,16 +56,16 @@ endfunc cortex_deimos_errata_report
* reported.
* ---------------------------------------------
*/
-.section .rodata.cortex_deimos_regs, "aS"
-cortex_deimos_regs: /* The ascii list of register names to be reported */
+.section .rodata.cortex_a77_regs, "aS"
+cortex_a77_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
-func cortex_deimos_cpu_reg_dump
- adr x6, cortex_deimos_regs
- mrs x8, CORTEX_DEIMOS_CPUECTLR_EL1
+func cortex_a77_cpu_reg_dump
+ adr x6, cortex_a77_regs
+ mrs x8, CORTEX_A77_CPUECTLR_EL1
ret
-endfunc cortex_deimos_cpu_reg_dump
+endfunc cortex_a77_cpu_reg_dump
-declare_cpu_ops cortex_deimos, CORTEX_DEIMOS_MIDR, \
+declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \
CPU_NO_RESET_FUNC, \
- cortex_deimos_core_pwr_dwn
+ cortex_a77_core_pwr_dwn