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author | John Tsichritzis <john.tsichritzis@arm.com> | 2019-03-04 16:41:26 +0000 |
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committer | John Tsichritzis <john.tsichritzis@arm.com> | 2019-03-14 11:31:43 +0000 |
commit | 8074448f096615a94d7bb54aa70a7dbfa6053ab4 (patch) | |
tree | 50f24e0524699e730ce6a76408624e1cb5c5c579 /lib/cpus | |
parent | 620d9832f96ffcaf86d38b703ca913438d6eea7c (diff) |
Apply variant 4 mitigation for Neoverse N1
This patch applies the new MSR instruction to directly set the
PSTATE.SSBS bit which controls speculative loads. This new instruction
is available at Neoverse N1 core so it's utilised.
Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Diffstat (limited to 'lib/cpus')
-rw-r--r-- | lib/cpus/aarch64/neoverse_n1.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index c6a5c08f..060c625d 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -46,6 +46,10 @@ endfunc check_errata_1043202 func neoverse_n1_reset_func mov x19, x30 + + /* Disables speculative loads */ + msr SSBS, xzr + bl cpu_get_rev_var mov x18, x0 |