diff options
| author | Soby Mathew <soby.mathew@arm.com> | 2016-12-06 12:10:51 +0000 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2016-12-12 17:57:37 +0000 |
| commit | 9f3ee61c904e4b6d2038086718c5ec4237d544a8 (patch) | |
| tree | a07820ccf5f8a93356566fec4b98fd1ae3a671ee /lib/cpus | |
| parent | 919ad05ecb8fab23f91a37783dc5f246847c7bd2 (diff) | |
AArch32: Fix the stack alignment issue
The AArch32 Procedure call Standard mandates that the stack must be aligned
to 8 byte boundary at external interfaces. This patch does the required
changes.
This problem was detected when a crash was encountered in
`psci_print_power_domain_map()` while printing 64 bit values. Aligning
the stack to 8 byte boundary resolved the problem.
Fixes ARM-Software/tf-issues#437
Change-Id: I517bd8203601bb88e9311bd36d477fb7b3efb292
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Diffstat (limited to 'lib/cpus')
| -rw-r--r-- | lib/cpus/aarch32/cortex_a32.S | 10 | ||||
| -rw-r--r-- | lib/cpus/aarch32/cpu_helpers.S | 10 |
2 files changed, 12 insertions, 8 deletions
diff --git a/lib/cpus/aarch32/cortex_a32.S b/lib/cpus/aarch32/cortex_a32.S index b51f997a..f2b85a31 100644 --- a/lib/cpus/aarch32/cortex_a32.S +++ b/lib/cpus/aarch32/cortex_a32.S @@ -72,7 +72,8 @@ endfunc cortex_a32_reset_func * ---------------------------------------------------- */ func cortex_a32_core_pwr_dwn - push {lr} + /* r12 is pushed to meet the 8 byte stack alignment requirement */ + push {r12, lr} /* Assert if cache is enabled */ #if ASM_ASSERTION @@ -92,7 +93,7 @@ func cortex_a32_core_pwr_dwn * Come out of intra cluster coherency * --------------------------------------------- */ - pop {lr} + pop {r12, lr} b cortex_a32_disable_smp endfunc cortex_a32_core_pwr_dwn @@ -102,7 +103,8 @@ endfunc cortex_a32_core_pwr_dwn * ------------------------------------------------------- */ func cortex_a32_cluster_pwr_dwn - push {lr} + /* r12 is pushed to meet the 8 byte stack alignment requirement */ + push {r12, lr} /* Assert if cache is enabled */ #if ASM_ASSERTION @@ -135,7 +137,7 @@ func cortex_a32_cluster_pwr_dwn * Come out of intra cluster coherency * --------------------------------------------- */ - pop {lr} + pop {r12, lr} b cortex_a32_disable_smp endfunc cortex_a32_cluster_pwr_dwn diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S index 042ffbdd..a4dfe5f2 100644 --- a/lib/cpus/aarch32/cpu_helpers.S +++ b/lib/cpus/aarch32/cpu_helpers.S @@ -76,9 +76,10 @@ endfunc reset_handler */ .globl prepare_core_pwr_dwn func prepare_core_pwr_dwn - push {lr} + /* r12 is pushed to meet the 8 byte stack alignment requirement */ + push {r12, lr} bl _cpu_data - pop {lr} + pop {r12, lr} ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] #if ASM_ASSERTION @@ -98,9 +99,10 @@ endfunc prepare_core_pwr_dwn */ .globl prepare_cluster_pwr_dwn func prepare_cluster_pwr_dwn - push {lr} + /* r12 is pushed to meet the 8 byte stack alignment requirement */ + push {r12, lr} bl _cpu_data - pop {lr} + pop {r12, lr} ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] #if ASM_ASSERTION |