diff options
| author | Douglas Raillard <douglas.raillard@arm.com> | 2017-03-07 16:36:14 +0000 |
|---|---|---|
| committer | Douglas Raillard <douglas.raillard@arm.com> | 2017-03-20 10:38:43 +0000 |
| commit | 355a5d03360802e2c7b8f09ffca641df0c9e47bf (patch) | |
| tree | 80a2804c6ff789e369be9d62637a8b0636044010 /lib/aarch64 | |
| parent | fa971fca2f16b3085499bc79066a8ba792841f13 (diff) | |
Replace ASM signed tests with unsigned
ge, lt, gt and le condition codes in assembly provide a signed test
whereas hs, lo, hi and ls provide the unsigned counterpart. Signed tests
should only be used when strictly necessary, as using them on logically
unsigned values can lead to inverting the test for high enough values.
All offsets, addresses and usually counters are actually unsigned
values, and should be tested as such.
Replace the occurrences of signed condition codes where it was
unnecessary by an unsigned test as the unsigned tests allow the full
range of unsigned values to be used without inverting the result with
some large operands.
Change-Id: I58b7e98d03e3a4476dfb45230311f296d224980a
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
Diffstat (limited to 'lib/aarch64')
| -rw-r--r-- | lib/aarch64/cache_helpers.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/aarch64/cache_helpers.S b/lib/aarch64/cache_helpers.S index 476b906e..acafea70 100644 --- a/lib/aarch64/cache_helpers.S +++ b/lib/aarch64/cache_helpers.S @@ -119,7 +119,7 @@ loop1: lsr x1, x0, x2 // extract cache type bits from clidr and x1, x1, #7 // mask the bits for current cache only cmp x1, #2 // see what cache we have at this level - b.lt level_done // nothing to do if no cache or icache + b.lo level_done // nothing to do if no cache or icache msr csselr_el1, x10 // select current cache level in csselr isb // isb to sych the new cssr&csidr @@ -144,10 +144,10 @@ loop3_\_op: orr w11, w9, w7 // combine cache, way and set number dc \_op, x11 subs w7, w7, w17 // decrement set number - b.ge loop3_\_op + b.hs loop3_\_op subs x9, x9, x16 // decrement way number - b.ge loop2_\_op + b.hs loop2_\_op b level_done .endm @@ -155,7 +155,7 @@ loop3_\_op: level_done: add x10, x10, #2 // increment cache number cmp x3, x10 - b.gt loop1 + b.hi loop1 msr csselr_el1, xzr // select cache level 0 in csselr dsb sy // barrier to complete final cache operation isb |