diff options
| author | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2017-04-20 09:58:28 +0100 |
|---|---|---|
| committer | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2017-04-20 09:58:28 +0100 |
| commit | 044bb2faabd7981af4ef419e1037fec28e5b3f8b (patch) | |
| tree | c5650c3f5431126e561ccb4a8b8f8554092b8a9d /lib/aarch64 | |
| parent | cc8b56322bb04569a5adf944774b16862782c95b (diff) | |
Remove build option `ASM_ASSERTION`
The build option `ENABLE_ASSERTIONS` should be used instead. That way
both C and ASM assertions can be enabled or disabled together.
All occurrences of `ASM_ASSERTION` in common code and ARM platforms have
been replaced by `ENABLE_ASSERTIONS`.
ASM_ASSERTION has been removed from the user guide.
Change-Id: I51f1991f11b9b7ff83e787c9a3270c274748ec6f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'lib/aarch64')
| -rw-r--r-- | lib/aarch64/misc_helpers.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S index 84265e0b..74550aa2 100644 --- a/lib/aarch64/misc_helpers.S +++ b/lib/aarch64/misc_helpers.S @@ -215,7 +215,7 @@ func zeromem_dczva tmp1 .req x4 tmp2 .req x5 -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS /* * Check for M bit (MMU enabled) of the current SCTLR_EL(1|3) * register value and panic if the MMU is disabled. @@ -228,7 +228,7 @@ func zeromem_dczva tst tmp1, #SCTLR_M_BIT ASM_ASSERT(ne) -#endif /* ASM_ASSERTION */ +#endif /* ENABLE_ASSERTIONS */ /* stop_address is the address past the last to zero */ add stop_address, cursor, length @@ -247,7 +247,7 @@ func zeromem_dczva mov tmp2, #(1 << 2) lsl block_size, tmp2, block_size -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS /* * Assumes block size is at least 16 bytes to avoid manual realignment * of the cursor at the end of the DCZVA loop. @@ -444,7 +444,7 @@ endfunc zeromem_dczva * -------------------------------------------------------------------------- */ func memcpy16 -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS orr x3, x0, x1 tst x3, #0xf ASM_ASSERT(eq) |