diff options
| author | Soby Mathew <soby.mathew@arm.com> | 2019-07-25 09:13:49 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-07-25 09:13:49 +0000 |
| commit | f7fb88f6682e1fa863f34a3ad8d0c130f2a30b63 (patch) | |
| tree | ff856a1c1a94245effe76f536d4c0805e19cca14 /include | |
| parent | d38613df9aa7d81505ff1da6e2905b3216d51ce5 (diff) | |
| parent | d200f2306463b28fc2650939ac9bcc0d701fa2d5 (diff) | |
Merge changes from topic "jts/spsr" into integration
* changes:
Refactor SPSR initialisation code
SSBS: init SPSR register with default SSBS value
Diffstat (limited to 'include')
| -rw-r--r-- | include/arch/aarch32/arch.h | 7 | ||||
| -rw-r--r-- | include/arch/aarch64/arch.h | 19 |
2 files changed, 17 insertions, 9 deletions
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 0db41458..34036d78 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -294,6 +294,8 @@ #define SPSR_MODE_SHIFT U(0) #define SPSR_MODE_MASK U(0x7) +#define SPSR_SSBS_BIT BIT_32(23) + #define DISABLE_ALL_EXCEPTIONS \ (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) @@ -384,11 +386,12 @@ #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) #define SPSR_MODE32(mode, isa, endian, aif) \ - (MODE_RW_32 << MODE_RW_SHIFT | \ + ((MODE_RW_32 << MODE_RW_SHIFT | \ ((mode) & MODE32_MASK) << MODE32_SHIFT | \ ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ - ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) + ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) & \ + (~(SPSR_SSBS_BIT))) /* * TTBR definitions diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index e4147d7e..fa857fb1 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -419,6 +419,9 @@ #define SPSR_M_AARCH64 U(0x0) #define SPSR_M_AARCH32 U(0x1) +#define SPSR_SSBS_BIT_AARCH64 BIT_64(12) +#define SPSR_SSBS_BIT_AARCH32 BIT_64(23) + #define DISABLE_ALL_EXCEPTIONS \ (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) @@ -543,18 +546,20 @@ #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) -#define SPSR_64(el, sp, daif) \ - ((MODE_RW_64 << MODE_RW_SHIFT) | \ - (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ - (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ - (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) +#define SPSR_64(el, sp, daif) \ + (((MODE_RW_64 << MODE_RW_SHIFT) | \ + (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ + (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ + (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ + (~(SPSR_SSBS_BIT_AARCH64))) #define SPSR_MODE32(mode, isa, endian, aif) \ - ((MODE_RW_32 << MODE_RW_SHIFT) | \ + (((MODE_RW_32 << MODE_RW_SHIFT) | \ (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ - (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) + (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ + (~(SPSR_SSBS_BIT_AARCH32))) /* * TTBR Definitions |