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authorBalint Dobszay <balint.dobszay@arm.com>2019-07-03 13:02:56 +0200
committerBalint Dobszay <balint.dobszay@arm.com>2019-07-10 12:14:20 +0200
commitf363deb6d409e64de70d25af868a91edb94c186c (patch)
tree1099d4b421ef3ed44a7e8ec87df7948b0701f0a5 /include
parent21bde92ff6d20ef2d3a2651fd729a1579232313b (diff)
Rename Cortex-Deimos to Cortex-A77
Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Diffstat (limited to 'include')
-rw-r--r--include/lib/cpus/aarch64/cortex_a77.h (renamed from include/lib/cpus/aarch64/cortex_deimos.h)15
1 files changed, 8 insertions, 7 deletions
diff --git a/include/lib/cpus/aarch64/cortex_deimos.h b/include/lib/cpus/aarch64/cortex_a77.h
index 9d024b67..0467ef3b 100644
--- a/include/lib/cpus/aarch64/cortex_deimos.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -4,22 +4,23 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef CORTEX_DEIMOS_H
-#define CORTEX_DEIMOS_H
+#ifndef CORTEX_A77_H
+#define CORTEX_A77_H
#include <lib/utils_def.h>
-#define CORTEX_DEIMOS_MIDR U(0x410FD0D0)
+/* Cortex-A77 MIDR */
+#define CORTEX_A77_MIDR U(0x410FD0D0)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
-#define CORTEX_DEIMOS_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions.
******************************************************************************/
-#define CORTEX_DEIMOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
+#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
-#endif /* CORTEX_DEIMOS_H */
+#endif /* CORTEX_A77_H */