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| author | Alexei Fedorov <Alexei.Fedorov@arm.com> | 2019-07-29 17:22:53 +0100 |
|---|---|---|
| committer | Paul Beesley <paul.beesley@arm.com> | 2019-08-16 11:30:37 +0000 |
| commit | ef430ff495aaf1c4bb5142570761351c6fe4b402 (patch) | |
| tree | 8be601b9ec40b0c19ec57aadb40818e7228cea24 /include | |
| parent | 300df53b9ada2ebe2d170748850975afe4858fee (diff) | |
FVP_Base_AEMv8A platform: Fix cache maintenance operations
This patch fixes FVP_Base_AEMv8A model hang issue with
ARMv8.4+ with cache modelling enabled configuration.
Incorrect L1 cache flush operation to PoU, using CLIDR_EL1
LoUIS field, which is required by the architecture to be
zero for ARMv8.4-A with ARMv8.4-S2FWB feature is replaced
with L1 to L2 and L2 to L3 (if L3 is present) cache flushes.
FVP_Base_AEMv8A model can be configured with L3 enabled by
setting `cluster0.l3cache-size` and `cluster1.l3cache-size`
to non-zero values, and presence of L3 is checked in
`aem_generic_core_pwr_dwn` function by reading
CLIDR_EL1.Ctype3 field value.
Change-Id: If3de3d4eb5ed409e5b4ccdbc2fe6d5a01894a9af
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/arch/aarch64/arch.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index fa857fb1..2b4ae1ad 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -112,6 +112,7 @@ /* CLIDR definitions */ #define LOUIS_SHIFT U(21) #define LOC_SHIFT U(24) +#define CTYPE_SHIFT(n) U(3 * (n - 1)) #define CLIDR_FIELD_WIDTH U(3) /* CSSELR definitions */ |