diff options
| author | Nitin Garg <nitin.garg@nxp.com> | 2017-06-07 15:47:04 -0500 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2020-03-07 15:36:00 +0800 |
| commit | e28150e16c774ea63d6df76e8c2e20c7360dbf61 (patch) | |
| tree | 1802705883142ee922eacc29993a29093a611d28 /include | |
| parent | ba12300cbf45b4d6a9acd484f4c1b80bef72b4ff (diff) | |
Enable CPU, FP, L2 retention counters to 64 cycles
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a35.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h index 5421478d..abef0428 100644 --- a/include/lib/cpus/aarch64/cortex_a35.h +++ b/include/lib/cpus/aarch64/cortex_a35.h @@ -12,6 +12,15 @@ /* Cortex-A35 Main ID register for revision 0 */ #define CORTEX_A35_MIDR U(0x410FD040) +/* Retention timer tick definitions */ +#define RETENTION_ENTRY_TICKS_2 0x1 +#define RETENTION_ENTRY_TICKS_8 0x2 +#define RETENTION_ENTRY_TICKS_32 0x3 +#define RETENTION_ENTRY_TICKS_64 0x4 +#define RETENTION_ENTRY_TICKS_128 0x5 +#define RETENTION_ENTRY_TICKS_256 0x6 +#define RETENTION_ENTRY_TICKS_512 0x7 + /******************************************************************************* * CPU Extended Control register specific definitions. * CPUECTLR_EL1 is an implementation-specific register. @@ -26,4 +35,28 @@ #define CORTEX_A35_CPUACTLR_EL1_ENDCCASCI (ULL(1) << 44) +#define CPUECTLR_CPU_RET_CTRL_SHIFT 0 +#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) + +#define CPUECTLR_FPU_RET_CTRL_SHIFT 3 +#define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT) + +/******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* + * L2 Extended Control register specific definitions. + ******************************************************************************/ +#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */ + +#define L2ECTLR_RET_CTRL_SHIFT 0 +#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) + +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* CORTEX_A35_H */ |