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| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2019-07-04 06:58:51 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-07-04 06:58:51 +0000 |
| commit | bb2d778c749ed772be8a2eb6f08356d2d03d9b1a (patch) | |
| tree | ccbf67ba40831b10dbc279d8f3f4464838eeb1c2 /include | |
| parent | b01e0ad5cd0e6a752ef6b3481b0040d7ecd780e1 (diff) | |
| parent | 7d6f751867a6c778280d931857663a3218251609 (diff) | |
Merge changes from topic "lw/n1_errata_fixes" into integration
* changes:
Removing redundant ISB instructions
Workaround for Neoverse N1 erratum 1275112
Workaround for Neoverse N1 erratum 1262888
Workaround for Neoverse N1 erratum 1262606
Workaround for Neoverse N1 erratum 1257314
Workaround for Neoverse N1 erratum 1220197
Workaround for Neoverse N1 erratum 1207823
Workaround for Neoverse N1 erratum 1165347
Workaround for Neoverse N1 erratum 1130799
Workaround for Neoverse N1 erratum 1073348
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index b66aeb8a..f90aa2ea 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -30,13 +30,29 @@ ******************************************************************************/ #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) +#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) + /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ +#define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) +#define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) + #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) + +#define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2 + +#define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) /* Instruction patching registers */ #define CPUPSELR_EL3 S3_6_C15_C8_0 |