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| author | Soby Mathew <soby.mathew@arm.com> | 2019-07-23 09:33:15 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-07-23 09:33:15 +0000 |
| commit | 53f3751b89b4dabb1975038b170fd8da9d2f14bd (patch) | |
| tree | da43745b5e1bcd7ca8c7fd37d5c4b241b13558d5 /include | |
| parent | 1d7dc63ca5e56fcf93210f4cba7c83683372a93c (diff) | |
| parent | 294f9ef9f95829dc16297a24df1e9e83234875b8 (diff) | |
Merge "Cortex_hercules: Introduce preliminary cpu support" into integration
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_hercules.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_hercules.h b/include/lib/cpus/aarch64/cortex_hercules.h new file mode 100644 index 00000000..86e8af03 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_hercules.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_HERCULES_H +#define CORTEX_HERCULES_H + +#include <lib/utils_def.h> + +#define CORTEX_HERCULES_MIDR U(0x410FD410) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_HERCULES_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_HERCULES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) + +#endif /* CORTEX_HERCULES_H */ |