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authorPetre-Ionut Tudor <petre-ionut.tudor@arm.com>2019-10-03 17:09:08 +0100
committerPetre-Ionut Tudor <petre-ionut.tudor@arm.com>2019-10-07 11:50:07 +0100
commit2a7adf2567aa103ced4a9a9b3ef8344935716d25 (patch)
tree5ce3f4cda4573251a7208f8c46f909bbd757d9b4 /include
parentcf9319f46a1dd17c842297a8aeb68059f6f3a06f (diff)
Explicitly disable the SPME bit in MDCR_EL3
Currently the MDCR_EL3 initialisation implicitly disables MDCR_EL3.SPME by using mov_imm. This patch makes the SPME bit more visible by explicitly disabling it and documenting its use in different versions of the architecture. Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Change-Id: I221fdf314f01622f46ac5aa43388f59fa17a29b3
Diffstat (limited to 'include')
-rw-r--r--include/arch/aarch64/el3_common_macros.S9
1 files changed, 8 insertions, 1 deletions
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index ee20d5b2..378e827c 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -113,11 +113,18 @@
* prohibited in Secure state. This bit is RES0 in versions of the
* architecture earlier than ARMv8.5, setting it to 1 doesn't have any
* effect on them.
+ *
+ * MDCR_EL3.SPME: Set to zero so that event counting by the programmable
+ * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2
+ * Debug is not implemented this bit does not have any effect on the
+ * counters unless there is support for the implementation defined
+ * authentication interface ExternalSecureNoninvasiveDebugEnabled().
* ---------------------------------------------------------------------
*/
mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \
- ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT))
+ ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | MDCR_TDA_BIT | \
+ MDCR_TPM_BIT))
msr mdcr_el3, x0