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| author | lauwal01 <lauren.wehrmeister@arm.com> | 2019-06-24 11:32:40 -0500 |
|---|---|---|
| committer | lauwal01 <lauren.wehrmeister@arm.com> | 2019-07-02 09:15:15 -0500 |
| commit | 2017ab241c6634ecc184f09a39e77a06146403b0 (patch) | |
| tree | 2df7811cdcf4159d4c36de40a65b57ed825e4811 /include | |
| parent | e34606f2e400c192bac3abeb9b2053b2c91ccd7c (diff) | |
Workaround for Neoverse N1 erratum 1165347
Neoverse N1 erratum 1165347 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUACTLR2_EL1 system register.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 9042d703..7950cd22 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -39,7 +39,9 @@ #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) |