diff options
| author | David Wang <david.wang@arm.com> | 2016-11-09 16:29:02 +0000 |
|---|---|---|
| committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-06-01 11:44:52 +0100 |
| commit | d40ab484d2d8cdcd400acae96d0f88c00e1c2bd2 (patch) | |
| tree | 7019b901daf559c0f772f1953f7c89cbcc716f02 /include | |
| parent | 2bd26faf62411c75111fea4b23c542865383b068 (diff) | |
Add support for Cortex-A75 and Cortex-A55 CPUs
Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit
(DSU). The power-down and power-up sequences are therefore mostly
managed in hardware, and required software operations are considerably
simpler.
Change-Id: I68b30e6e1ebe7c041d5e67f39c59f08575fc7ecc
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a55.h | 22 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a75.h | 22 |
2 files changed, 44 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h new file mode 100644 index 00000000..293f2b24 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a55.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_A55_H__ +#define __CORTEX_A55_H__ + +/* Cortex-A55 MIDR for revision 0 */ +#define CORTEX_A55_MIDR 0x410fd050 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 + +/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ +#define CORTEX_A55_CORE_PWRDN_EN_MASK 0x1 + +#endif /* __CORTEX_A55_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h new file mode 100644 index 00000000..1ffe20bb --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a75.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_A75_H__ +#define __CORTEX_A75_H__ + +/* Cortex-A75 MIDR */ +#define CORTEX_A75_MIDR 0x410fd0a0 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4 + +/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ +#define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1 + +#endif /* __CORTEX_A75_H__ */ |