diff options
| author | danh-arm <dan.handley@arm.com> | 2017-06-05 14:41:20 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-06-05 14:41:20 +0100 |
| commit | 03dd6391f9c4d54197d83842def5d1a5321cacbb (patch) | |
| tree | a2dddae5e4227b18914b5f35207271462cc9ab76 /include | |
| parent | 4d96cad5b200e2f94720249dd0b2ae896c67d966 (diff) | |
| parent | d40ab484d2d8cdcd400acae96d0f88c00e1c2bd2 (diff) | |
Merge pull request #960 from jeenu-arm/cpu-libs
Add support for Cortex-A75 and Cortex-A55 CPUs
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a55.h | 22 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a75.h | 22 |
2 files changed, 44 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h new file mode 100644 index 00000000..293f2b24 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a55.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_A55_H__ +#define __CORTEX_A55_H__ + +/* Cortex-A55 MIDR for revision 0 */ +#define CORTEX_A55_MIDR 0x410fd050 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 + +/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ +#define CORTEX_A55_CORE_PWRDN_EN_MASK 0x1 + +#endif /* __CORTEX_A55_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h new file mode 100644 index 00000000..1ffe20bb --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a75.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_A75_H__ +#define __CORTEX_A75_H__ + +/* Cortex-A75 MIDR */ +#define CORTEX_A75_MIDR 0x410fd0a0 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4 + +/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ +#define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1 + +#endif /* __CORTEX_A75_H__ */ |