diff options
| author | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2018-01-03 10:48:59 +0000 |
|---|---|---|
| committer | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2018-01-18 10:36:25 +0000 |
| commit | e4b34efa18f1cac10aa8541bc0a1dbab49886009 (patch) | |
| tree | ba91227084b8bf3ccc28434cafa3466c5e9d9afd /include | |
| parent | 7343505d9661ab6481e99fa96d60f2a8447a4565 (diff) | |
Workaround for CVE-2017-5715 for Cortex A9, A15 and A17
A per-cpu vbar is installed that implements the workaround by
invalidating the branch target buffer (BTB) directly in the case of A9
and A17 and indirectly by invalidating the icache in the case of A15.
For Cortex A57 and A72 there is currently no workaround implemented
when EL3 is in AArch32 mode so report it as missing.
For other vulnerable CPUs (e.g. Cortex A73 and Cortex A75), there are
no changes since there is currently no upstream AArch32 EL3 support
for these CPUs.
Change-Id: Ib42c6ef0b3c9ff2878a9e53839de497ff736258f
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a15.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/lib/cpus/aarch32/cortex_a15.h b/include/lib/cpus/aarch32/cortex_a15.h index 905c139d..0f01a433 100644 --- a/include/lib/cpus/aarch32/cortex_a15.h +++ b/include/lib/cpus/aarch32/cortex_a15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,6 +15,7 @@ /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ +#define CORTEX_A15_ACTLR_INV_BTB_BIT (1 << 0) #define CORTEX_A15_ACTLR_SMP_BIT (1 << 6) #endif /* __CORTEX_A15_H__ */ |