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| author | Paul Beesley <paul.beesley@arm.com> | 2019-05-29 11:29:12 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-05-29 11:29:12 +0000 |
| commit | 84167417db275b8fd529dae7a4cf87ab8c41a414 (patch) | |
| tree | 65ab5a6ce696029230e99ea9f615326a2c3cf236 /include/lib | |
| parent | 5a408104902fdcb03ea11266d948a0460174c8a7 (diff) | |
| parent | 9af07df0506af9a4230bafb3e74c769f0de3ec9a (diff) | |
Merge "Cortex-A55: workarounds for errata 1221012" into integration
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a55.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h index feac1d2f..60ed957d 100644 --- a/include/lib/cpus/aarch64/cortex_a55.h +++ b/include/lib/cpus/aarch64/cortex_a55.h @@ -39,4 +39,10 @@ /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ #define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1) +/* Instruction patching registers */ +#define CPUPSELR_EL3 S3_6_C15_C8_0 +#define CPUPCR_EL3 S3_6_C15_C8_1 +#define CPUPOR_EL3 S3_6_C15_C8_2 +#define CPUPMR_EL3 S3_6_C15_C8_3 + #endif /* CORTEX_A55_H */ |