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| author | lauwal01 <lauren.wehrmeister@arm.com> | 2019-06-24 11:23:50 -0500 |
|---|---|---|
| committer | lauwal01 <lauren.wehrmeister@arm.com> | 2019-07-02 09:13:31 -0500 |
| commit | a601afe1585e8d53afb7c1ea87d0ba7a5bb85bd3 (patch) | |
| tree | 2136ae3823d11d40f1304965245e73d5f3355651 /include/lib | |
| parent | b73d296d747663ecd31caf30ddcebf4a99f39abf (diff) | |
Workaround for Neoverse N1 erratum 1073348
Neoverse N1 erratum 1073348 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which disables static prediction.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index b66aeb8a..9048f437 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -33,6 +33,10 @@ /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ +#define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) + #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) |