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| author | Alexei Fedorov <Alexei.Fedorov@arm.com> | 2019-04-04 16:26:34 +0100 |
|---|---|---|
| committer | Alexei Fedorov <Alexei.Fedorov@arm.com> | 2019-04-08 14:48:55 +0100 |
| commit | 9ccc5a573363660b1f537dda6bd37327e8f1a2ea (patch) | |
| tree | a3c5799ee0bb0d40993a3cb47cceda52aebd5569 /include/lib | |
| parent | 8a08e27232d0c1b906fd2f3e4b3b7a90661a50b9 (diff) | |
Add support for Cortex-A76AE CPU
Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a76ae.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a76ae.h b/include/lib/cpus/aarch64/cortex_a76ae.h new file mode 100644 index 00000000..9e34efba --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a76ae.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A76AE_H +#define CORTEX_A76AE_H + +#include <lib/utils_def.h> + +/* Cortex-A76AE MIDR for revision 0 */ +#define CORTEX_A76AE_MIDR U(0x410FD0E0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A76AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7 + +/* Definitions of register field mask in CORTEX_A76AE_CPUPWRCTLR_EL1 */ +#define CORTEX_A76AE_CORE_PWRDN_EN_MASK U(0x1) + +#define CORTEX_A76AE_CPUECTLR_EL1 S3_0_C15_C1_4 + +#endif /* CORTEX_A76AE_H */ |