diff options
| author | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-05-28 09:52:48 +0100 |
|---|---|---|
| committer | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-05-28 14:19:04 +0100 |
| commit | 9af07df0506af9a4230bafb3e74c769f0de3ec9a (patch) | |
| tree | 0af915983c704825a23efa901c12e736fd2890e1 /include/lib | |
| parent | ced1711297347f24fee45e75e73c7767507a0982 (diff) | |
Cortex-A55: workarounds for errata 1221012
The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integrator.
Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a55.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h index feac1d2f..60ed957d 100644 --- a/include/lib/cpus/aarch64/cortex_a55.h +++ b/include/lib/cpus/aarch64/cortex_a55.h @@ -39,4 +39,10 @@ /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ #define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1) +/* Instruction patching registers */ +#define CPUPSELR_EL3 S3_6_C15_C8_0 +#define CPUPCR_EL3 S3_6_C15_C8_1 +#define CPUPOR_EL3 S3_6_C15_C8_2 +#define CPUPMR_EL3 S3_6_C15_C8_3 + #endif /* CORTEX_A55_H */ |