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| author | Andre Przywara <andre.przywara@arm.com> | 2019-05-20 14:57:06 +0100 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2019-06-06 14:27:37 +0100 |
| commit | 5f5d0763875218893d3831a685886c17d20be940 (patch) | |
| tree | 777151cf55daa16119f9035dd5b6d9fa1d7730b8 /include/lib | |
| parent | 49d969bbb3ca7e738bc6ef560e44c0047a9925cc (diff) | |
Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703
Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in
older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined CPUACTLR2_EL1
system register, which will disable the load-bypass-store feature.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html
Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index ed5f136d..b66aeb8a 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -35,7 +35,8 @@ ******************************************************************************/ #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 -#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) /* Instruction patching registers */ #define CPUPSELR_EL3 S3_6_C15_C8_0 |