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| author | lauwal01 <lauren.wehrmeister@arm.com> | 2019-06-24 11:42:02 -0500 |
|---|---|---|
| committer | lauwal01 <lauren.wehrmeister@arm.com> | 2019-07-02 09:16:32 -0500 |
| commit | 335b3c79c79dcfc04e9776ce2e21c3b16aa6febf (patch) | |
| tree | 7af15c666969446e6b24b141048d5edad882101e /include/lib | |
| parent | 9eceb020d79614cf41d64f6eae4086f3b5390203 (diff) | |
Workaround for Neoverse N1 erratum 1257314
Neoverse N1 erratum 1257314 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR3_EL1 system register, which prevents parallel
execution of divide and square root instructions.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 952ae6eb..0e9ddb8f 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -48,6 +48,9 @@ #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) +#define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2 + +#define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) /* Instruction patching registers */ #define CPUPSELR_EL3 S3_6_C15_C8_0 |