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| author | lauwal01 <lauren.wehrmeister@arm.com> | 2019-06-24 11:47:30 -0500 |
|---|---|---|
| committer | lauwal01 <lauren.wehrmeister@arm.com> | 2019-07-02 09:17:17 -0500 |
| commit | 11c48370bd8c1dfdf5221a073a26615904c94413 (patch) | |
| tree | 00db093dd1481dc07924f494580abf82f326554b /include/lib | |
| parent | 411f4959b45b7a072b567dadf33b110936f14f32 (diff) | |
Workaround for Neoverse N1 erratum 1262888
Neoverse N1 erratum 1262888 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 8f0ecf2b..f90aa2ea 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -31,6 +31,7 @@ #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) +#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) /******************************************************************************* * CPU Auxiliary Control register specific definitions. |