include: add U()/ULL() macros for constants

This patch uses the U() and ULL() macros for constants, to fix some
of the signed-ness defects flagged by the MISRA scanner.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

1 files changed, 87 insertions, 87 deletions

diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h
index 7959bb78..3a3d7aaa 100644
--- a/include/drivers/arm/gic_v2.h
+++ b/include/drivers/arm/gic_v2.h
@@ -15,115 +15,115 @@
 #error " The legacy ARM GIC driver is deprecated."
 #endif
 
-#define GIC400_NUM_SPIS		480
-#define MAX_PPIS		14
-#define MAX_SGIS		16
-
-#define MIN_SGI_ID		0
-#define MIN_PPI_ID		16
-#define MIN_SPI_ID		32
-
-#define GRP0			0
-#define GRP1			1
-#define GIC_PRI_MASK		0xff
-#define GIC_HIGHEST_SEC_PRIORITY 0
-#define GIC_LOWEST_SEC_PRIORITY	127
-#define GIC_HIGHEST_NS_PRIORITY	128
-#define GIC_LOWEST_NS_PRIORITY	254 /* 255 would disable an interrupt */
-#define GIC_SPURIOUS_INTERRUPT	1023
-#define GIC_TARGET_CPU_MASK	0xff
-
-#define ENABLE_GRP0		(1 << 0)
-#define ENABLE_GRP1		(1 << 1)
+#define GIC400_NUM_SPIS		U(480)
+#define MAX_PPIS		U(14)
+#define MAX_SGIS		U(16)
+
+#define MIN_SGI_ID		U(0)
+#define MIN_PPI_ID		U(16)
+#define MIN_SPI_ID		U(32)
+
+#define GRP0			U(0)
+#define GRP1			U(1)
+#define GIC_PRI_MASK		U(0xff)
+#define GIC_HIGHEST_SEC_PRIORITY U(0)
+#define GIC_LOWEST_SEC_PRIORITY	U(127)
+#define GIC_HIGHEST_NS_PRIORITY	U(128)
+#define GIC_LOWEST_NS_PRIORITY	U(254) /* 255 would disable an interrupt */
+#define GIC_SPURIOUS_INTERRUPT	U(1023)
+#define GIC_TARGET_CPU_MASK	U(0xff)
+
+#define ENABLE_GRP0		(U(1) << 0)
+#define ENABLE_GRP1		(U(1) << 1)
 
 /* Distributor interface definitions */
-#define GICD_CTLR		0x0
-#define GICD_TYPER		0x4
-#define GICD_IGROUPR		0x80
-#define GICD_ISENABLER		0x100
-#define GICD_ICENABLER		0x180
-#define GICD_ISPENDR		0x200
-#define GICD_ICPENDR		0x280
-#define GICD_ISACTIVER		0x300
-#define GICD_ICACTIVER		0x380
-#define GICD_IPRIORITYR		0x400
-#define GICD_ITARGETSR		0x800
-#define GICD_ICFGR		0xC00
-#define GICD_SGIR		0xF00
-#define GICD_CPENDSGIR		0xF10
-#define GICD_SPENDSGIR		0xF20
-
-#define IGROUPR_SHIFT		5
-#define ISENABLER_SHIFT		5
+#define GICD_CTLR		U(0x0)
+#define GICD_TYPER		U(0x4)
+#define GICD_IGROUPR		U(0x80)
+#define GICD_ISENABLER		U(0x100)
+#define GICD_ICENABLER		U(0x180)
+#define GICD_ISPENDR		U(0x200)
+#define GICD_ICPENDR		U(0x280)
+#define GICD_ISACTIVER		U(0x300)
+#define GICD_ICACTIVER		U(0x380)
+#define GICD_IPRIORITYR		U(0x400)
+#define GICD_ITARGETSR		U(0x800)
+#define GICD_ICFGR		U(0xC00)
+#define GICD_SGIR		U(0xF00)
+#define GICD_CPENDSGIR		U(0xF10)
+#define GICD_SPENDSGIR		U(0xF20)
+
+#define IGROUPR_SHIFT		U(5)
+#define ISENABLER_SHIFT		U(5)
 #define ICENABLER_SHIFT		ISENABLER_SHIFT
-#define ISPENDR_SHIFT		5
+#define ISPENDR_SHIFT		U(5)
 #define ICPENDR_SHIFT		ISPENDR_SHIFT
-#define ISACTIVER_SHIFT		5
+#define ISACTIVER_SHIFT		U(5)
 #define ICACTIVER_SHIFT		ISACTIVER_SHIFT
-#define IPRIORITYR_SHIFT	2
-#define ITARGETSR_SHIFT		2
-#define ICFGR_SHIFT		4
-#define CPENDSGIR_SHIFT		2
+#define IPRIORITYR_SHIFT	U(2)
+#define ITARGETSR_SHIFT		U(2)
+#define ICFGR_SHIFT		U(4)
+#define CPENDSGIR_SHIFT		U(2)
 #define SPENDSGIR_SHIFT		CPENDSGIR_SHIFT
 
 /* GICD_TYPER bit definitions */
-#define IT_LINES_NO_MASK	0x1f
+#define IT_LINES_NO_MASK	U(0x1f)
 
 /* Physical CPU Interface registers */
-#define GICC_CTLR		0x0
-#define GICC_PMR		0x4
-#define GICC_BPR		0x8
-#define GICC_IAR		0xC
-#define GICC_EOIR		0x10
-#define GICC_RPR		0x14
-#define GICC_HPPIR		0x18
-#define GICC_AHPPIR		0x28
-#define GICC_IIDR		0xFC
-#define GICC_DIR		0x1000
+#define GICC_CTLR		U(0x0)
+#define GICC_PMR		U(0x4)
+#define GICC_BPR		U(0x8)
+#define GICC_IAR		U(0xC)
+#define GICC_EOIR		U(0x10)
+#define GICC_RPR		U(0x14)
+#define GICC_HPPIR		U(0x18)
+#define GICC_AHPPIR		U(0x28)
+#define GICC_IIDR		U(0xFC)
+#define GICC_DIR		U(0x1000)
 #define GICC_PRIODROP           GICC_EOIR
 
 /* Common CPU Interface definitions */
-#define INT_ID_MASK		0x3ff
+#define INT_ID_MASK		U(0x3ff)
 
 /* GICC_CTLR bit definitions */
-#define EOI_MODE_NS		(1 << 10)
-#define EOI_MODE_S		(1 << 9)
-#define IRQ_BYP_DIS_GRP1	(1 << 8)
-#define FIQ_BYP_DIS_GRP1	(1 << 7)
-#define IRQ_BYP_DIS_GRP0	(1 << 6)
-#define FIQ_BYP_DIS_GRP0	(1 << 5)
-#define CBPR			(1 << 4)
-#define FIQ_EN			(1 << 3)
-#define ACK_CTL			(1 << 2)
+#define EOI_MODE_NS		(U(1) << 10)
+#define EOI_MODE_S		(U(1) << 9)
+#define IRQ_BYP_DIS_GRP1	(U(1) << 8)
+#define FIQ_BYP_DIS_GRP1	(U(1) << 7)
+#define IRQ_BYP_DIS_GRP0	(U(1) << 6)
+#define FIQ_BYP_DIS_GRP0	(U(1) << 5)
+#define CBPR			(U(1) << 4)
+#define FIQ_EN			(U(1) << 3)
+#define ACK_CTL			(U(1) << 2)
 
 /* GICC_IIDR bit masks and shifts */
-#define GICC_IIDR_PID_SHIFT	20
-#define GICC_IIDR_ARCH_SHIFT	16
-#define GICC_IIDR_REV_SHIFT	12
-#define GICC_IIDR_IMP_SHIFT	0
+#define GICC_IIDR_PID_SHIFT	U(20)
+#define GICC_IIDR_ARCH_SHIFT	U(16)
+#define GICC_IIDR_REV_SHIFT	U(12)
+#define GICC_IIDR_IMP_SHIFT	U(0)
 
-#define GICC_IIDR_PID_MASK	0xfff
-#define GICC_IIDR_ARCH_MASK	0xf
-#define GICC_IIDR_REV_MASK	0xf
-#define GICC_IIDR_IMP_MASK	0xfff
+#define GICC_IIDR_PID_MASK	U(0xfff)
+#define GICC_IIDR_ARCH_MASK	U(0xf)
+#define GICC_IIDR_REV_MASK	U(0xf)
+#define GICC_IIDR_IMP_MASK	U(0xfff)
 
 /* HYP view virtual CPU Interface registers */
-#define GICH_CTL		0x0
-#define GICH_VTR		0x4
-#define GICH_ELRSR0		0x30
-#define GICH_ELRSR1		0x34
-#define GICH_APR0		0xF0
-#define GICH_LR_BASE		0x100
+#define GICH_CTL		U(0x0)
+#define GICH_VTR		U(0x4)
+#define GICH_ELRSR0		U(0x30)
+#define GICH_ELRSR1		U(0x34)
+#define GICH_APR0		U(0xF0)
+#define GICH_LR_BASE		U(0x100)
 
 /* Virtual CPU Interface registers */
-#define GICV_CTL		0x0
-#define GICV_PRIMASK		0x4
-#define GICV_BP			0x8
-#define GICV_INTACK		0xC
-#define GICV_EOI		0x10
-#define GICV_RUNNINGPRI		0x14
-#define GICV_HIGHESTPEND	0x18
-#define GICV_DEACTIVATE		0x1000
+#define GICV_CTL		U(0x0)
+#define GICV_PRIMASK		U(0x4)
+#define GICV_BP			U(0x8)
+#define GICV_INTACK		U(0xC)
+#define GICV_EOI		U(0x10)
+#define GICV_RUNNINGPRI		U(0x14)
+#define GICV_HIGHESTPEND	U(0x18)
+#define GICV_DEACTIVATE		U(0x1000)
 
 #ifndef __ASSEMBLY__