diff options
| author | Sathees Balya <sathees.balya@arm.com> | 2019-01-25 11:36:01 +0000 |
|---|---|---|
| committer | Sathees Balya <sathees.balya@arm.com> | 2019-01-30 11:17:38 +0000 |
| commit | cedfa04ba58841b5c547b409e435c0bdafa4c912 (patch) | |
| tree | f7de45c25aed76ee15d2ee3930e3bbdeb624fd65 /include/arch | |
| parent | 83a2285ec8d5e4bdbf12481b441489eed5bb6018 (diff) | |
lib/xlat_tables: Add support for ARMv8.4-TTST
ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the
size of translation tables by increasing the maximum permitted value
of the T1SZ and T0SZ fields in TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2 and
VSTCR_EL2.
This feature is supported in AArch64 state only.
This patch adds support for this feature to both versions of the
translation tables library. It also removes the static build time
checks for virtual address space size checks to runtime assertions.
Change-Id: I4e8cebc197ec1c2092dc7d307486616786e6c093
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
Diffstat (limited to 'include/arch')
| -rw-r--r-- | include/arch/aarch64/arch.h | 5 | ||||
| -rw-r--r-- | include/arch/aarch64/arch_features.h | 6 |
2 files changed, 11 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 9e2bffac..76c3e277 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -204,6 +204,10 @@ /* ID_AA64MMFR2_EL1 definitions */ #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + +#define ID_AA64MMFR2_EL1_ST_SHIFT U(28) +#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) + #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) @@ -427,6 +431,7 @@ #define TCR_TxSZ_MIN ULL(16) #define TCR_TxSZ_MAX ULL(39) +#define TCR_TxSZ_MAX_TTST ULL(48) /* (internal) physical address size bits in EL3/EL1 */ #define TCR_PS_BITS_4GB ULL(0x0) diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 2b09ba07..9bf43bf8 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -17,4 +17,10 @@ static inline bool is_armv8_2_ttcnp_present(void) ID_AA64MMFR2_EL1_CNP_MASK) != 0U; } +static inline bool is_armv8_4_ttst_present(void) +{ + return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) & + ID_AA64MMFR2_EL1_ST_MASK) == 1U; +} + #endif /* ARCH_FEATURES_H */ |