diff options
| author | John Tsichritzis <john.tsichritzis@arm.com> | 2019-03-04 16:41:26 +0000 |
|---|---|---|
| committer | John Tsichritzis <john.tsichritzis@arm.com> | 2019-03-14 11:31:43 +0000 |
| commit | 8074448f096615a94d7bb54aa70a7dbfa6053ab4 (patch) | |
| tree | 50f24e0524699e730ce6a76408624e1cb5c5c579 /include/arch | |
| parent | 620d9832f96ffcaf86d38b703ca913438d6eea7c (diff) | |
Apply variant 4 mitigation for Neoverse N1
This patch applies the new MSR instruction to directly set the
PSTATE.SSBS bit which controls speculative loads. This new instruction
is available at Neoverse N1 core so it's utilised.
Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Diffstat (limited to 'include/arch')
| -rw-r--r-- | include/arch/aarch64/arch.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index debe8722..d3c5beaa 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -843,4 +843,9 @@ #define DIT S3_3_C4_C2_5 #define DIT_BIT BIT(24) +/******************************************************************************* + * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field + ******************************************************************************/ +#define SSBS S3_3_C4_C2_6 + #endif /* ARCH_H */ |