diff options
| author | Yann Gautier <yann.gautier@st.com> | 2019-02-15 17:33:27 +0100 |
|---|---|---|
| committer | Yann Gautier <yann.gautier@st.com> | 2019-02-20 17:34:21 +0100 |
| commit | b053a22e8a538d3ee6114c0ce7f25fa49f0302d8 (patch) | |
| tree | f8818474819c18d8dc75d9c36289deeb386be285 /fdts | |
| parent | 774b4a8190ccb73d9c9deefba0c0fd3878be55ce (diff) | |
stm32mp1: add minimal support for co-processor Cortex-M4
STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4.
The support for Cortex-M4 clocks is added when configuring the clock tree.
Some minimal security features to allow communications between A7 and M4
are also added.
Change-Id: I60417e244a476f60a2758f4969700b2684056665
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Diffstat (limited to 'fdts')
| -rw-r--r-- | fdts/stm32mp157a-dk1.dts | 2 | ||||
| -rw-r--r-- | fdts/stm32mp157c-ed1.dts | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/fdts/stm32mp157a-dk1.dts b/fdts/stm32mp157a-dk1.dts index 0314171f..cf0fe288 100644 --- a/fdts/stm32mp157a-dk1.dts +++ b/fdts/stm32mp157a-dk1.dts @@ -204,6 +204,7 @@ st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P + CLK_MCU_PLL3P CLK_PLL12_HSE CLK_PLL3_HSE CLK_PLL4_HSE @@ -215,6 +216,7 @@ st,clkdiv = < 1 /*MPU*/ 0 /*AXI*/ + 0 /*MCU*/ 1 /*APB1*/ 1 /*APB2*/ 1 /*APB3*/ diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts index 5d8817f6..0fadffbd 100644 --- a/fdts/stm32mp157c-ed1.dts +++ b/fdts/stm32mp157c-ed1.dts @@ -224,6 +224,7 @@ st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P + CLK_MCU_PLL3P CLK_PLL12_HSE CLK_PLL3_HSE CLK_PLL4_HSE @@ -235,6 +236,7 @@ st,clkdiv = < 1 /*MPU*/ 0 /*AXI*/ + 0 /*MCU*/ 1 /*APB1*/ 1 /*APB2*/ 1 /*APB3*/ |