diff options
| author | Antonio Borneo <antonio.borneo@st.com> | 2019-07-29 14:46:16 +0200 |
|---|---|---|
| committer | Yann Gautier <yann.gautier@st.com> | 2019-10-03 11:17:40 +0200 |
| commit | 2dc9fe70da6788ff69856ed247b10a59173431c3 (patch) | |
| tree | bf9ccdb0c877be6a4d43a097d19f42ad811a21c5 /fdts | |
| parent | 57f4b6f83974b17e0aae04e17f9d95a5659ac88b (diff) | |
fdts: stm32mp1: move FDCAN to PLL4_R
LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe and pretends to use it later.
This change fixes the issue by moving the FDCAN to PLL4_R,
leaving the LTDC alone on PLL4_Q.
Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58
Diffstat (limited to 'fdts')
| -rw-r--r-- | fdts/stm32mp157a-avenger96.dts | 2 | ||||
| -rw-r--r-- | fdts/stm32mp157a-dk1.dts | 2 | ||||
| -rw-r--r-- | fdts/stm32mp157c-ed1.dts | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/fdts/stm32mp157a-avenger96.dts b/fdts/stm32mp157a-avenger96.dts index 9df72b44..907940c7 100644 --- a/fdts/stm32mp157a-avenger96.dts +++ b/fdts/stm32mp157a-avenger96.dts @@ -246,7 +246,7 @@ CLK_UART6_HSI CLK_UART78_HSI CLK_SPDIF_PLL4P - CLK_FDCAN_PLL4Q + CLK_FDCAN_PLL4R CLK_SAI1_PLL3Q CLK_SAI2_PLL3Q CLK_SAI3_PLL3Q diff --git a/fdts/stm32mp157a-dk1.dts b/fdts/stm32mp157a-dk1.dts index b17d5019..4ea83f7c 100644 --- a/fdts/stm32mp157a-dk1.dts +++ b/fdts/stm32mp157a-dk1.dts @@ -266,7 +266,7 @@ CLK_UART6_HSI CLK_UART78_HSI CLK_SPDIF_PLL4P - CLK_FDCAN_PLL4Q + CLK_FDCAN_PLL4R CLK_SAI1_PLL3Q CLK_SAI2_PLL3Q CLK_SAI3_PLL3Q diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts index ed55725b..77949255 100644 --- a/fdts/stm32mp157c-ed1.dts +++ b/fdts/stm32mp157c-ed1.dts @@ -272,7 +272,7 @@ CLK_UART6_HSI CLK_UART78_HSI CLK_SPDIF_PLL4P - CLK_FDCAN_PLL4Q + CLK_FDCAN_PLL4R CLK_SAI1_PLL3Q CLK_SAI2_PLL3Q CLK_SAI3_PLL3Q |