diff options
author | Yann Gautier <yann.gautier@st.com> | 2019-06-04 17:24:36 +0200 |
---|---|---|
committer | Yann Gautier <yann.gautier@st.com> | 2019-06-17 14:03:51 +0200 |
commit | f237822f0b003dc5bec54d8c4ee961597a11116c (patch) | |
tree | 48b3bbc84cbfd3be7c5b080e0b54305a17b7a50e /fdts/stm32mp157-pinctrl.dtsi | |
parent | 0a016775ad068d53639b97441e884ddd074e220d (diff) |
fdts: stm32mp1: realign device tree files with internal devs
Update DDR parameters to version 1.45.
Remove useless sdmmc1_dir_pins_b node.
Add USART3 and UART7 nodes.
Correct a PMIC value for USB regulator.
Add TIMER12, TIMER15, CRYP, HASH and USBOTG_HS nodes.
Update DTSI file for SDMMC compatible, but overwrite it with the former
name.
Move BSEC board_id node to boards DTS files, as this OTP is specific to
STMicroelectronics boards.
Change-Id: If4d2fe090c6a8368afe8e21e5ac70579911d3939
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Diffstat (limited to 'fdts/stm32mp157-pinctrl.dtsi')
-rw-r--r-- | fdts/stm32mp157-pinctrl.dtsi | 43 |
1 files changed, 28 insertions, 15 deletions
diff --git a/fdts/stm32mp157-pinctrl.dtsi b/fdts/stm32mp157-pinctrl.dtsi index c7553ca5..8e480b2c 100644 --- a/fdts/stm32mp157-pinctrl.dtsi +++ b/fdts/stm32mp157-pinctrl.dtsi @@ -214,21 +214,6 @@ }; }; - sdmmc1_dir_pins_b: sdmmc1-dir-1 { - pins1 { - pinmux = <STM32_PINMUX('E', 12, AF8)>, /* SDMMC1_D0DIR */ - <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ - slew-rate = <3>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ @@ -286,6 +271,19 @@ }; }; + uart7_pins_a: uart7-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */ + bias-disable; + }; + }; + usart3_pins_a: usart3-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ @@ -300,6 +298,21 @@ bias-disable; }; }; + + usart3_pins_b: usart3-1 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ + <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ + bias-disable; + }; + }; }; pinctrl_z: pin-controller-z@54004000 { |