diff options
author | Yann Gautier <yann.gautier@st.com> | 2019-06-04 17:24:36 +0200 |
---|---|---|
committer | Yann Gautier <yann.gautier@st.com> | 2019-06-17 14:03:51 +0200 |
commit | f237822f0b003dc5bec54d8c4ee961597a11116c (patch) | |
tree | 48b3bbc84cbfd3be7c5b080e0b54305a17b7a50e /fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | |
parent | 0a016775ad068d53639b97441e884ddd074e220d (diff) |
fdts: stm32mp1: realign device tree files with internal devs
Update DDR parameters to version 1.45.
Remove useless sdmmc1_dir_pins_b node.
Add USART3 and UART7 nodes.
Correct a PMIC value for USB regulator.
Add TIMER12, TIMER15, CRYP, HASH and USBOTG_HS nodes.
Update DTSI file for SDMMC compatible, but overwrite it with the former
name.
Move BSEC board_id node to boards DTS files, as this OTP is specific to
STMicroelectronics boards.
Change-Id: If4d2fe090c6a8368afe8e21e5ac70579911d3939
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Diffstat (limited to 'fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi')
-rw-r--r-- | fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi index 16b8cf62..11e8f2be 100644 --- a/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi +++ b/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - */ -/* STM32MP157C DK1/DK2 BOARD configuration + * + * STM32MP157C DK1/DK2 BOARD configuration * 1x DDR3L 4Gb, 16-bit, 533MHz. * Reference used NT5CC256M16DP-DI from NANYA * @@ -16,8 +16,7 @@ * address mapping : RBC * Tc > + 85C : N */ - -#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.41" +#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45" #define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x20000000 @@ -90,7 +89,7 @@ #define DDR_PTR2 0x042DA068 #define DDR_ACIOCR 0x10400812 #define DDR_DXCCR 0x00000C40 -#define DDR_DSGCR 0xF200001F +#define DDR_DSGCR 0xF200011F #define DDR_DCR 0x0000000B #define DDR_DTPR0 0x38D488D0 #define DDR_DTPR1 0x098B00D8 @@ -109,11 +108,11 @@ #define DDR_DX1DLLCR 0x40000000 #define DDR_DX1DQTR 0xFFFFFFFF #define DDR_DX1DQSTR 0x3DB02000 -#define DDR_DX2GCR 0x0000CE81 +#define DDR_DX2GCR 0x0000CE80 #define DDR_DX2DLLCR 0x40000000 #define DDR_DX2DQTR 0xFFFFFFFF #define DDR_DX2DQSTR 0x3DB02000 -#define DDR_DX3GCR 0x0000CE81 +#define DDR_DX3GCR 0x0000CE80 #define DDR_DX3DLLCR 0x40000000 #define DDR_DX3DQTR 0xFFFFFFFF #define DDR_DX3DQSTR 0x3DB02000 |