diff options
| author | Roberto Vargas <roberto.vargas@arm.com> | 2018-04-23 14:44:54 +0100 |
|---|---|---|
| committer | Roberto Vargas <roberto.vargas@arm.com> | 2018-04-24 08:30:01 +0100 |
| commit | e230f4d54d5eafa7d1d8ab413fbc7c68b9520042 (patch) | |
| tree | f46a91c99d06952562a2f1988fedbfc7202e9a47 /fdts/fvp-foundation-motherboard.dtsi | |
| parent | 7f6d8f49aa916a526c2ce227606cc51eebd0c950 (diff) | |
Remove dtc warnings
DTC generates warnings when unit names begin with 0, or
when a node containing a reg or range property doesn't have a unit name
in the node name. This patch fixes those cases.
Change-Id: If24ec68ef3034fb3fcefb96c5625c47a0bbd8474
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Diffstat (limited to 'fdts/fvp-foundation-motherboard.dtsi')
| -rw-r--r-- | fdts/fvp-foundation-motherboard.dtsi | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/fdts/fvp-foundation-motherboard.dtsi b/fdts/fvp-foundation-motherboard.dtsi index ae7237b7..9ee5b645 100644 --- a/fdts/fvp-foundation-motherboard.dtsi +++ b/fdts/fvp-foundation-motherboard.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,14 +44,14 @@ #size-cells = <1>; ranges = <0 3 0 0x200000>; - v2m_sysreg: sysreg@010000 { + v2m_sysreg: sysreg@10000 { compatible = "arm,vexpress-sysreg"; reg = <0x010000 0x1000>; gpio-controller; #gpio-cells = <2>; }; - v2m_sysctl: sysctl@020000 { + v2m_sysctl: sysctl@20000 { compatible = "arm,sp810", "arm,primecell"; reg = <0x020000 0x1000>; clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; @@ -60,7 +60,7 @@ clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; }; - v2m_serial0: uart@090000 { + v2m_serial0: uart@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <0 5 4>; @@ -68,7 +68,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@0a0000 { + v2m_serial1: uart@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <0 6 4>; @@ -76,7 +76,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@0b0000 { + v2m_serial2: uart@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <0 7 4>; @@ -84,7 +84,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@0c0000 { + v2m_serial3: uart@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <0 8 4>; @@ -92,7 +92,7 @@ clock-names = "uartclk", "apb_pclk"; }; - wdt@0f0000 { + wdt@f0000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0f0000 0x1000>; interrupts = <0 0 4>; @@ -124,7 +124,7 @@ clock-names = "apb_pclk"; }; - virtio_block@0130000 { + virtio_block@130000 { compatible = "virtio,mmio"; reg = <0x130000 0x1000>; interrupts = <0 0x2a 4>; |