diff options
author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-07-19 17:27:49 +0100 |
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committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-08-01 14:33:47 +0100 |
commit | 1bdbdc3b3f3068797a1539eacff727592762d5b9 (patch) | |
tree | c38b1338b7be1f2e34dd04a5a55fdc55b8fb7fe6 /fdts/fvp-base-gicv3-psci-1t.dts | |
parent | 11ad8f208db42f7729b0ce2bd16c631c293e665c (diff) |
Add Linux DTS for FVP with threaded CPUs
In contrast with the non-multi-threading DTS, this enumerates MPIDR
values shifted by one affinity level to the left. The newly added DTS
reflects CPUs with a single thread in them.
Since both DTS files are the same apart from MPIDR contents, the common
bits have been moved to a separate file that's then included from the
top-level DTS files. The multi-threading version only updates the MPIDR
contents.
Change-Id: Id225cd93574f764171df8962ac76f42fcb6bba4b
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'fdts/fvp-base-gicv3-psci-1t.dts')
-rw-r--r-- | fdts/fvp-base-gicv3-psci-1t.dts | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/fdts/fvp-base-gicv3-psci-1t.dts b/fdts/fvp-base-gicv3-psci-1t.dts new file mode 100644 index 00000000..36fbd444 --- /dev/null +++ b/fdts/fvp-base-gicv3-psci-1t.dts @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +/include/ "fvp-base-gicv3-psci-common.dtsi" + +&CPU0 { + reg = <0x0 0x0>; +}; + +&CPU1 { + reg = <0x0 0x100>; +}; + +&CPU2 { + reg = <0x0 0x200>; +}; + +&CPU3 { + reg = <0x0 0x300>; +}; + +&CPU4 { + reg = <0x0 0x10000>; +}; + +&CPU5 { + reg = <0x0 0x10100>; +}; + +&CPU6 { + reg = <0x0 0x10200>; +}; + +&CPU7 { + reg = <0x0 0x10300>; +}; |