Merge changes from topic "jc/shift-overflow" into integration

* changes:
  Enable -Wshift-overflow=2 to check for undefined shift behavior
  Update base code to not rely on undefined overflow behaviour
  Update hisilicon drivers to not rely on undefined overflow behaviour
  Update synopsys drivers to not rely on undefined overflow behaviour
  Update imx platform to not rely on undefined overflow behaviour
  Update mediatek platform to not rely on undefined overflow behaviour
  Update layerscape platform to not rely on undefined overflow behaviour
  Update intel platform to not rely on undefined overflow behaviour
  Update rockchip platform to not rely on undefined overflow behaviour
  Update renesas platform to not rely on undefined overflow behaviour
  Update meson platform to not rely on undefined overflow behaviour
  Update marvell platform to not rely on undefined overflow behaviour

7 files changed, 14 insertions, 13 deletions

diff --git a/drivers/marvell/mci.c b/drivers/marvell/mci.c
index 3a9859c9..06fe88e1 100644
--- a/drivers/marvell/mci.c
+++ b/drivers/marvell/mci.c
@@ -245,7 +245,7 @@
 				MCI_PHY_CTRL_PHY_ADDR_MSB_OFFSET)
 #define MCI_PHY_CTRL_PIDI_MODE_OFFSET			31
 #define MCI_PHY_CTRL_PIDI_MODE				\
-				(1 << MCI_PHY_CTRL_PIDI_MODE_OFFSET)
+				(1U << MCI_PHY_CTRL_PIDI_MODE_OFFSET)
 
 /* Number of times to wait for the MCI link ready after MCI configurations
  * Normally takes 34-35 successive reads
diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c
index d7d73731..b4b4e0c8 100644
--- a/drivers/marvell/mochi/cp110_setup.c
+++ b/drivers/marvell/mochi/cp110_setup.c
@@ -56,11 +56,11 @@
 				(0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET)
 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET	16
 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK	\
-				(0xffff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
+				(0xffffu << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
 
 #define MVEBU_SAMPLE_AT_RESET_REG	(0x440600)
 #define SAR_PCIE1_CLK_CFG_OFFSET	31
-#define SAR_PCIE1_CLK_CFG_MASK		(0x1 << SAR_PCIE1_CLK_CFG_OFFSET)
+#define SAR_PCIE1_CLK_CFG_MASK		(0x1u << SAR_PCIE1_CLK_CFG_OFFSET)
 #define SAR_PCIE0_CLK_CFG_OFFSET	30
 #define SAR_PCIE0_CLK_CFG_MASK		(0x1 << SAR_PCIE0_CLK_CFG_OFFSET)
 #define SAR_I2C_INIT_EN_OFFSET		24
diff --git a/drivers/meson/gxl/crypto/sha_dma.c b/drivers/meson/gxl/crypto/sha_dma.c
index 565099c4..a969dea7 100644
--- a/drivers/meson/gxl/crypto/sha_dma.c
+++ b/drivers/meson/gxl/crypto/sha_dma.c
@@ -104,8 +104,8 @@ struct asd_desc {
 #define ASD_DESC_ERR_SET(d, v)					\
 	(ASD_DESC_SET((d)->cfg, v, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF))
 
-#define ASD_DESC_OWNER_OFF 31
-#define ASD_DESC_OWNER_MASK 0x1
+#define ASD_DESC_OWNER_OFF 31u
+#define ASD_DESC_OWNER_MASK 0x1u
 #define ASD_DESC_OWNER(d)					\
 	(ASD_DESC_GET((d)->cfg, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF))
 #define ASD_DESC_OWNER_SET(d, v)				\
@@ -126,7 +126,7 @@ static void asd_compute_sha(struct asd_ctx *ctx, void *data, size_t len,
 	assert((uintptr_t)&desc == (uintptr_t)&desc);
 
 	ASD_DESC_LEN_SET(&desc, len);
-	ASD_DESC_OWNER_SET(&desc, 1);
+	ASD_DESC_OWNER_SET(&desc, 1u);
 	ASD_DESC_ENCONLY_SET(&desc, 1);
 	ASD_DESC_EOD_SET(&desc, 1);
 	if (ctx->started == 0) {
diff --git a/drivers/renesas/rcar/cpld/ulcb_cpld.c b/drivers/renesas/rcar/cpld/ulcb_cpld.c
index 48308537..5ffb2e19 100644
--- a/drivers/renesas/rcar/cpld/ulcb_cpld.c
+++ b/drivers/renesas/rcar/cpld/ulcb_cpld.c
@@ -68,7 +68,7 @@ static void cpld_write(uint8_t addr, uint32_t data)
 
 	for (i = 0; i < 32; i++) {
 		/* MSB first */
-		gpio_set_value(GPIO_OUTDT6, MOSI, data & (1 << 31));
+		gpio_set_value(GPIO_OUTDT6, MOSI, data & (1U << 31));
 		gpio_set_value(GPIO_OUTDT6, SCLK, 1);
 		data <<= 1;
 		gpio_set_value(GPIO_OUTDT6, SCLK, 0);
diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c
index d97e593b..f4c9d3ab 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.c
+++ b/drivers/renesas/rcar/pwrc/pwrc.c
@@ -763,10 +763,10 @@ uint32_t rcar_pwrc_get_cluster(void)
 
 	reg = mmio_read_32(RCAR_PRR);
 
-	if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
+	if (reg & (1U << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
 		return RCAR_CLUSTER_CA57;
 
-	if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
+	if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
 		return RCAR_CLUSTER_CA53;
 
 	return RCAR_CLUSTER_A53A57;
@@ -810,7 +810,7 @@ uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
 
 count_ca57:
 	if (IS_A53A57(c) || IS_CA57(c)) {
-		if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
+		if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
 			goto done;
 
 		for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) {
diff --git a/drivers/renesas/rcar/pwrc/pwrc.h b/drivers/renesas/rcar/pwrc/pwrc.h
index cfb35ff9..e67c6ef2 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.h
+++ b/drivers/renesas/rcar/pwrc/pwrc.h
@@ -15,7 +15,7 @@
 
 #define PWKUPR_WEN		(1ull << 31)
 
-#define PSYSR_AFF_L2		(1 << 31)
+#define PSYSR_AFF_L2		(1U << 31)
 #define PSYSR_AFF_L1		(1 << 30)
 #define PSYSR_AFF_L0		(1 << 29)
 #define PSYSR_WEN		(1 << 28)
diff --git a/drivers/synopsys/emmc/dw_mmc.c b/drivers/synopsys/emmc/dw_mmc.c
index e84a9355..04f46732 100644
--- a/drivers/synopsys/emmc/dw_mmc.c
+++ b/drivers/synopsys/emmc/dw_mmc.c
@@ -14,6 +14,7 @@
 #include <drivers/delay_timer.h>
 #include <drivers/mmc.h>
 #include <drivers/synopsys/dw_mmc.h>
+#include <lib/utils_def.h>
 #include <lib/mmio.h>
 
 #define DWMMC_CTRL			(0x00)
@@ -55,7 +56,7 @@
 
 #define DWMMC_CMDARG			(0x28)
 #define DWMMC_CMD			(0x2c)
-#define CMD_START			(1 << 31)
+#define CMD_START			(U(1) << 31)
 #define CMD_USE_HOLD_REG		(1 << 29)	/* 0 if SDR50/100 */
 #define CMD_UPDATE_CLK_ONLY		(1 << 21)
 #define CMD_SEND_INIT			(1 << 15)
@@ -100,7 +101,7 @@
 #define IDMAC_DES0_CH			(1 << 4)
 #define IDMAC_DES0_ER			(1 << 5)
 #define IDMAC_DES0_CES			(1 << 30)
-#define IDMAC_DES0_OWN			(1 << 31)
+#define IDMAC_DES0_OWN			(U(1) << 31)
 #define IDMAC_DES1_BS1(x)		((x) & 0x1fff)
 #define IDMAC_DES2_BS2(x)		(((x) & 0x1fff) << 13)