diff options
author | Yann Gautier <yann.gautier@st.com> | 2019-02-14 11:13:39 +0100 |
---|---|---|
committer | Yann Gautier <yann.gautier@st.com> | 2019-02-14 11:20:23 +0100 |
commit | 3f9c97842e5780e0e21f8eb36844c8154635c8c4 (patch) | |
tree | 5133e202c726138211e000550147376d67068125 /drivers/st | |
parent | c9d75b3cf98c7f2a78d3f916bcf9e2b3a2c55967 (diff) |
stm32mp1: make functions and macros more common
Mainly remove suffix 1 from prefix stm32mp1 in several macros and functions
that can be used in drivers shared by different platforms.
Change-Id: I2295c44f5b1edac7e80a93c0e8dfd671b36e88e7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Diffstat (limited to 'drivers/st')
-rw-r--r-- | drivers/st/clk/stm32mp1_clk.c | 10 | ||||
-rw-r--r-- | drivers/st/ddr/stm32mp1_ddr.c | 2 | ||||
-rw-r--r-- | drivers/st/ddr/stm32mp1_ram.c | 46 | ||||
-rw-r--r-- | drivers/st/gpio/stm32_gpio.c | 8 | ||||
-rw-r--r-- | drivers/st/mmc/stm32_sdmmc2.c | 20 | ||||
-rw-r--r-- | drivers/st/pmic/stm32mp_pmic.c | 2 | ||||
-rw-r--r-- | drivers/st/reset/stm32mp1_reset.c | 8 |
7 files changed, 48 insertions, 48 deletions
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c index e4cc9b9e..02866a21 100644 --- a/drivers/st/clk/stm32mp1_clk.c +++ b/drivers/st/clk/stm32mp1_clk.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -777,7 +777,7 @@ static unsigned long stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) return clock; } -bool stm32mp1_clk_is_enabled(unsigned long id) +bool stm32mp_clk_is_enabled(unsigned long id) { struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; const struct stm32mp1_clk_gate *gate = priv->data->gate; @@ -791,7 +791,7 @@ bool stm32mp1_clk_is_enabled(unsigned long id) BIT(gate[i].bit)) != 0U); } -int stm32mp1_clk_enable(unsigned long id) +int stm32mp_clk_enable(unsigned long id) { struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; const struct stm32mp1_clk_gate *gate = priv->data->gate; @@ -810,7 +810,7 @@ int stm32mp1_clk_enable(unsigned long id) return 0; } -int stm32mp1_clk_disable(unsigned long id) +int stm32mp_clk_disable(unsigned long id) { struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; const struct stm32mp1_clk_gate *gate = priv->data->gate; @@ -831,7 +831,7 @@ int stm32mp1_clk_disable(unsigned long id) return 0; } -unsigned long stm32mp1_clk_get_rate(unsigned long id) +unsigned long stm32mp_clk_get_rate(unsigned long id) { struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data; int p = stm32mp1_clk_get_parent(priv, id); diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c index 79aff6e7..b9347540 100644 --- a/drivers/st/ddr/stm32mp1_ddr.c +++ b/drivers/st/ddr/stm32mp1_ddr.c @@ -639,7 +639,7 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv) */ /* Change Bypass Mode Frequency Range */ - if (stm32mp1_clk_get_rate(DDRPHYC) < 100000000U) { + if (stm32mp_clk_get_rate(DDRPHYC) < 100000000U) { mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr, DDRPHYC_DLLGCR_BPS200); } else { diff --git a/drivers/st/ddr/stm32mp1_ram.c b/drivers/st/ddr/stm32mp1_ram.c index e65fbeaa..532062e0 100644 --- a/drivers/st/ddr/stm32mp1_ram.c +++ b/drivers/st/ddr/stm32mp1_ram.c @@ -31,7 +31,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) ddr_enable_clock(); - ddrphy_clk = stm32mp1_clk_get_rate(DDRPHYC); + ddrphy_clk = stm32mp_clk_get_rate(DDRPHYC); VERBOSE("DDR: mem_speed (%d kHz), RCC %ld kHz\n", mem_speed, ddrphy_clk / 1000U); @@ -65,10 +65,10 @@ static uint32_t ddr_test_data_bus(void) uint32_t pattern; for (pattern = 1U; pattern != 0U; pattern <<= 1) { - mmio_write_32(STM32MP1_DDR_BASE, pattern); + mmio_write_32(STM32MP_DDR_BASE, pattern); - if (mmio_read_32(STM32MP1_DDR_BASE) != pattern) { - return (uint32_t)STM32MP1_DDR_BASE; + if (mmio_read_32(STM32MP_DDR_BASE) != pattern) { + return (uint32_t)STM32MP_DDR_BASE; } } @@ -92,44 +92,44 @@ static uint32_t ddr_test_addr_bus(void) /* Write the default pattern at each of the power-of-two offsets. */ for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; offset <<= 1) { - mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)offset, + mmio_write_32(STM32MP_DDR_BASE + (uint32_t)offset, DDR_PATTERN); } /* Check for address bits stuck high. */ - mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, + mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_ANTIPATTERN); for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; offset <<= 1) { - if (mmio_read_32(STM32MP1_DDR_BASE + (uint32_t)offset) != + if (mmio_read_32(STM32MP_DDR_BASE + (uint32_t)offset) != DDR_PATTERN) { - return (uint32_t)(STM32MP1_DDR_BASE + offset); + return (uint32_t)(STM32MP_DDR_BASE + offset); } } - mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN); + mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN); /* Check for address bits stuck low or shorted. */ for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U; testoffset <<= 1) { - mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, + mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_ANTIPATTERN); - if (mmio_read_32(STM32MP1_DDR_BASE) != DDR_PATTERN) { - return STM32MP1_DDR_BASE; + if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { + return STM32MP_DDR_BASE; } for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; offset <<= 1) { - if ((mmio_read_32(STM32MP1_DDR_BASE + + if ((mmio_read_32(STM32MP_DDR_BASE + (uint32_t)offset) != DDR_PATTERN) && (offset != testoffset)) { - return (uint32_t)(STM32MP1_DDR_BASE + offset); + return (uint32_t)(STM32MP_DDR_BASE + offset); } } - mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, + mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN); } @@ -147,13 +147,13 @@ static uint32_t ddr_check_size(void) { uint32_t offset = sizeof(uint32_t); - mmio_write_32(STM32MP1_DDR_BASE, DDR_PATTERN); + mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN); - while (offset < STM32MP1_DDR_MAX_SIZE) { - mmio_write_32(STM32MP1_DDR_BASE + offset, DDR_ANTIPATTERN); + while (offset < STM32MP_DDR_MAX_SIZE) { + mmio_write_32(STM32MP_DDR_BASE + offset, DDR_ANTIPATTERN); dsb(); - if (mmio_read_32(STM32MP1_DDR_BASE) != DDR_PATTERN) { + if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { break; } @@ -240,15 +240,15 @@ static int stm32mp1_ddr_setup(void) } } - if (!stm32mp1_clk_is_enabled(RTCAPB)) { + if (!stm32mp_clk_is_enabled(RTCAPB)) { tamp_clk_off = 1; - if (stm32mp1_clk_enable(RTCAPB) != 0) { + if (stm32mp_clk_enable(RTCAPB) != 0) { return -EINVAL; } } if (tamp_clk_off != 0U) { - if (stm32mp1_clk_disable(RTCAPB) != 0) { + if (stm32mp_clk_disable(RTCAPB) != 0) { return -EINVAL; } } @@ -306,7 +306,7 @@ int stm32mp1_ddr_probe(void) priv->pwr = PWR_BASE; priv->rcc = RCC_BASE; - priv->info.base = STM32MP1_DDR_BASE; + priv->info.base = STM32MP_DDR_BASE; priv->info.size = 0; return stm32mp1_ddr_setup(); diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c index 5fee82cd..1d8111a1 100644 --- a/drivers/st/gpio/stm32_gpio.c +++ b/drivers/st/gpio/stm32_gpio.c @@ -208,7 +208,7 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed, assert(pin <= GPIO_PIN_MAX); - stm32mp1_clk_enable(clock); + stm32mp_clk_enable(clock); mmio_clrbits_32(base + GPIO_MODE_OFFSET, ((uint32_t)GPIO_MODE_MASK << (pin << 1))); @@ -254,7 +254,7 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed, VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank, mmio_read_32(base + GPIO_AFRH_OFFSET)); - stm32mp1_clk_disable(clock); + stm32mp_clk_disable(clock); } void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure) @@ -264,7 +264,7 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure) assert(pin <= GPIO_PIN_MAX); - stm32mp1_clk_enable(clock); + stm32mp_clk_enable(clock); if (secure) { mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); @@ -272,5 +272,5 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure) mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); } - stm32mp1_clk_disable(clock); + stm32mp_clk_disable(clock); } diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c index 57812d89..10fd5f5d 100644 --- a/drivers/st/mmc/stm32_sdmmc2.c +++ b/drivers/st/mmc/stm32_sdmmc2.c @@ -19,9 +19,9 @@ #include <drivers/mmc.h> #include <drivers/st/stm32_gpio.h> #include <drivers/st/stm32_sdmmc2.h> +#include <drivers/st/stm32mp_reset.h> #include <drivers/st/stm32mp1_clk.h> #include <drivers/st/stm32mp1_rcc.h> -#include <drivers/st/stm32mp1_reset.h> #include <dt-bindings/clock/stm32mp1-clks.h> #include <dt-bindings/reset/stm32mp1-resets.h> #include <lib/mmio.h> @@ -159,7 +159,7 @@ static void stm32_sdmmc2_init(void) uintptr_t base = sdmmc2_params.reg_base; clock_div = div_round_up(sdmmc2_params.clk_rate, - STM32MP1_MMC_INIT_FREQ * 2); + STM32MP_MMC_INIT_FREQ * 2); mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | sdmmc2_params.negedge | @@ -429,15 +429,15 @@ static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { if (max_bus_freq >= 52000000U) { - max_freq = STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ; + max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ; } else { - max_freq = STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ; + max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ; } } else { if (max_bus_freq >= 50000000U) { - max_freq = STM32MP1_SD_HIGH_SPEED_MAX_FREQ; + max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ; } else { - max_freq = STM32MP1_SD_NORMAL_SPEED_MAX_FREQ; + max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ; } } @@ -720,19 +720,19 @@ int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) return -ENOMEM; } - ret = stm32mp1_clk_enable(sdmmc2_params.clock_id); + ret = stm32mp_clk_enable(sdmmc2_params.clock_id); if (ret != 0) { ERROR("%s: clock %d failed\n", __func__, sdmmc2_params.clock_id); return ret; } - stm32mp1_reset_assert(sdmmc2_params.reset_id); + stm32mp_reset_assert(sdmmc2_params.reset_id); udelay(2); - stm32mp1_reset_deassert(sdmmc2_params.reset_id); + stm32mp_reset_deassert(sdmmc2_params.reset_id); mdelay(1); - sdmmc2_params.clk_rate = stm32mp1_clk_get_rate(sdmmc2_params.clock_id); + sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id); return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, sdmmc2_params.bus_width, sdmmc2_params.flags, diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c index 6beabc15..eb5c6e66 100644 --- a/drivers/st/pmic/stm32mp_pmic.c +++ b/drivers/st/pmic/stm32mp_pmic.c @@ -167,7 +167,7 @@ void initialize_pmic_i2c(void) panic(); } - if (stm32mp1_clk_enable((uint32_t)i2c_info.clock) < 0) { + if (stm32mp_clk_enable((uint32_t)i2c_info.clock) < 0) { ERROR("I2C clock enable failed\n"); panic(); } diff --git a/drivers/st/reset/stm32mp1_reset.c b/drivers/st/reset/stm32mp1_reset.c index f58e10b2..aac74e15 100644 --- a/drivers/st/reset/stm32mp1_reset.c +++ b/drivers/st/reset/stm32mp1_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, STMicroelectronics - All Rights Reserved + * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,14 +10,14 @@ #include <common/bl_common.h> #include <common/debug.h> +#include <drivers/st/stm32mp_reset.h> #include <drivers/st/stm32mp1_rcc.h> -#include <drivers/st/stm32mp1_reset.h> #include <lib/mmio.h> #include <lib/utils_def.h> #define RST_CLR_OFFSET 4U -void stm32mp1_reset_assert(uint32_t id) +void stm32mp_reset_assert(uint32_t id) { uint32_t offset = (id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t); uint32_t bit = id % (uint32_t)__LONG_BIT; @@ -28,7 +28,7 @@ void stm32mp1_reset_assert(uint32_t id) } } -void stm32mp1_reset_deassert(uint32_t id) +void stm32mp_reset_deassert(uint32_t id) { uint32_t offset = ((id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t)) + RST_CLR_OFFSET; |