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authorSandrine Bailleux <sandrine.bailleux@arm.com>2018-10-31 13:41:47 +0100
committerSandrine Bailleux <sandrine.bailleux@arm.com>2018-11-06 17:28:20 +0100
commitb56ec680800c851382777118e868c6a6d4996729 (patch)
tree966f2baa553b3969b7f8daa4d88615acfd9d0b76 /drivers/arm
parent638d2b5141193e08e22f1aecb592396dbf05856d (diff)
Remove _tzc_get_max_top_addr() function
This function was needed at the time where we didn't have the compiler_rt lib. An AArch32-specific variant was provided to handle the 64-bit shift operation in 32-bit. This is no longer needed. Change-Id: Ibab709a95e3a723ae2eeaddf873dba70ff2012b3 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Diffstat (limited to 'drivers/arm')
-rw-r--r--drivers/arm/tzc/tzc400.c4
-rw-r--r--drivers/arm/tzc/tzc_common_private.h35
-rw-r--r--drivers/arm/tzc/tzc_dmc500.c2
3 files changed, 3 insertions, 38 deletions
diff --git a/drivers/arm/tzc/tzc400.c b/drivers/arm/tzc/tzc400.c
index 763eba73..d27b0102 100644
--- a/drivers/arm/tzc/tzc400.c
+++ b/drivers/arm/tzc/tzc400.c
@@ -182,8 +182,8 @@ void tzc400_configure_region(unsigned int filters,
* Do address range check based on TZC configuration. A 64bit address is
* the max and expected case.
*/
- assert(((region_top <= _tzc_get_max_top_addr(tzc400.addr_width)) &&
- (region_base < region_top)));
+ assert((region_top <= (UINT64_MAX >> (64U - tzc400.addr_width))) &&
+ (region_base < region_top));
/* region_base and (region_top + 1) must be 4KB aligned */
assert(((region_base | (region_top + 1U)) & (4096U - 1U)) == 0U);
diff --git a/drivers/arm/tzc/tzc_common_private.h b/drivers/arm/tzc/tzc_common_private.h
index 5fbea92b..efac8507 100644
--- a/drivers/arm/tzc/tzc_common_private.h
+++ b/drivers/arm/tzc/tzc_common_private.h
@@ -180,39 +180,4 @@ static inline unsigned int _tzc_read_peripheral_id(uintptr_t base)
return id;
}
-#if ENABLE_ASSERTIONS
-#ifdef AARCH32
-static inline unsigned long long _tzc_get_max_top_addr(unsigned int addr_width)
-{
- /*
- * Assume at least 32 bit wide address and initialize the max.
- * This function doesn't use 64-bit integer arithmetic to avoid
- * having to implement additional compiler library functions.
- */
- unsigned long long addr_mask = 0xFFFFFFFFU;
- uint32_t *addr_ptr = (uint32_t *)&addr_mask;
-
- assert(addr_width >= 32U);
-
- /* This logic works only on little - endian platforms */
- assert((read_sctlr() & SCTLR_EE_BIT) == 0U);
-
- /*
- * If required address width is greater than 32, populate the higher
- * 32 bits of the 64 bit field with the max address.
- */
- if (addr_width > 32U)
- *(addr_ptr + 1U) = ((1U << (addr_width - 32U)) - 1U);
-
- return addr_mask;
-}
-#else
-static inline unsigned long long _tzc_get_max_top_addr(unsigned int addr_width)
-{
- return UINT64_MAX >> (64U - addr_width);
-}
-#endif /* AARCH32 */
-
-#endif /* ENABLE_ASSERTIONS */
-
#endif /* TZC_COMMON_PRIVATE_H */
diff --git a/drivers/arm/tzc/tzc_dmc500.c b/drivers/arm/tzc/tzc_dmc500.c
index 3e6c7838..f0aba9c1 100644
--- a/drivers/arm/tzc/tzc_dmc500.c
+++ b/drivers/arm/tzc/tzc_dmc500.c
@@ -188,7 +188,7 @@ void tzc_dmc500_configure_region(unsigned int region_no,
* Do address range check based on DMC-TZ configuration. A 43bit address
* is the max and expected case.
*/
- assert(((region_top <= _tzc_get_max_top_addr(43)) &&
+ assert(((region_top <= (UINT64_MAX >> (64U - 43U))) &&
(region_base < region_top)));
/* region_base and (region_top + 1) must be 4KB aligned */