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| author | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2018-08-21 16:12:29 +0100 |
|---|---|---|
| committer | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2018-08-30 09:22:34 +0100 |
| commit | 6d5f0631a63a7df7ad936fea4e6cd9edd25a9be0 (patch) | |
| tree | d5f9dc44b2be0a97e71257e5c6fc935c2ac3e097 /drivers/arm | |
| parent | 819df3fc0942c96ffecca0fcb0e370806957b5bc (diff) | |
drivers: smmu: Fix MISRA defects
Change-Id: I2954a99d5b72069bcb7bac9d6926c6209d6ba881
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'drivers/arm')
| -rw-r--r-- | drivers/arm/smmu/smmu_v3.c | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/drivers/arm/smmu/smmu_v3.c b/drivers/arm/smmu/smmu_v3.c index 7b017e30..ddb99634 100644 --- a/drivers/arm/smmu/smmu_v3.c +++ b/drivers/arm/smmu/smmu_v3.c @@ -1,15 +1,12 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <mmio.h> #include <smmu_v3.h> - -/* Test for pending invalidate */ -#define INVAL_PENDING(_base) \ - smmuv3_read_s_init(_base) & SMMU_S_INIT_INV_ALL_MASK +#include <stdbool.h> static inline uint32_t smmuv3_read_s_idr1(uintptr_t base) { @@ -26,6 +23,12 @@ static inline void smmuv3_write_s_init(uintptr_t base, uint32_t value) mmio_write_32(base + SMMU_S_INIT, value); } +/* Test for pending invalidate */ +static inline bool smmuv3_inval_pending(uintptr_t base) +{ + return (smmuv3_read_s_init(base) & SMMU_S_INIT_INV_ALL_MASK) != 0U; +} + /* * Initialize the SMMU by invalidating all secure caches and TLBs. * @@ -41,14 +44,14 @@ int smmuv3_init(uintptr_t smmu_base) * SMMU_S_INIT register is accessed. */ idr1_reg = smmuv3_read_s_idr1(smmu_base); - if (!((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) & - SMMU_S_IDR1_SECURE_IMPL_MASK)) { + if (((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) & + SMMU_S_IDR1_SECURE_IMPL_MASK) == 0U) { return -1; } /* Initiate invalidation, and wait for it to finish */ smmuv3_write_s_init(smmu_base, SMMU_S_INIT_INV_ALL_MASK); - while (INVAL_PENDING(smmu_base)) + while (smmuv3_inval_pending(smmu_base)) ; return 0; |