diff options
| author | Andrew F. Davis <afd@ti.com> | 2018-07-26 13:50:14 -0500 |
|---|---|---|
| committer | Andrew F. Davis <afd@ti.com> | 2018-07-26 14:14:07 -0500 |
| commit | 9262eb54db167d432fe0856b5451039a1b948f6f (patch) | |
| tree | 9ce35fce4d93209bcb4998f2ac0ca3fea510f2ef /drivers/arm/gic | |
| parent | 39a8fa70f0d9a1d7093020fcd00e565e99a2306f (diff) | |
GIC: Do not flush cache when unneeded
When a platform enables its caches before it initializes the
GICC/GICR interface then explicit cache maintenance is not
needed. Remove these here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Diffstat (limited to 'drivers/arm/gic')
| -rw-r--r-- | drivers/arm/gic/v2/gicv2_main.c | 7 | ||||
| -rw-r--r-- | drivers/arm/gic/v3/gicv3_main.c | 5 |
2 files changed, 7 insertions, 5 deletions
diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index bbe73fb9..7cf6c76e 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c @@ -221,9 +221,10 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) * enabled. When the secondary CPU boots up, it initializes the * GICC/GICR interface with the caches disabled. Hence flush the * driver_data to ensure coherency. This is not required if the - * platform has HW_ASSISTED_COHERENCY enabled. + * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY + * enabled. */ -#if !HW_ASSISTED_COHERENCY +#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); #endif @@ -360,7 +361,7 @@ void gicv2_set_pe_target_mask(unsigned int proc_num) if (driver_data->target_masks[proc_num] == 0) { driver_data->target_masks[proc_num] = gicv2_get_cpuif_id(driver_data->gicd_base); -#if !HW_ASSISTED_COHERENCY +#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) /* * PEs only update their own masks. Primary updates it with * caches on. But because secondaries does it with caches off, diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index 83d030a8..40d14aba 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -147,9 +147,10 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) * enabled. When the secondary CPU boots up, it initializes the * GICC/GICR interface with the caches disabled. Hence flush the * driver data to ensure coherency. This is not required if the - * platform has HW_ASSISTED_COHERENCY enabled. + * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY + * enabled. */ -#if !HW_ASSISTED_COHERENCY +#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) flush_dcache_range((uintptr_t) &gicv3_driver_data, sizeof(gicv3_driver_data)); flush_dcache_range((uintptr_t) gicv3_driver_data, |