doc: Final, pre-release fixes and updates

A small set of misc changes to ensure correctness before the v2.2
release tagging.

Change-Id: I888840b9483ea1a1633d204fbbc0f9594072101e
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

5 files changed, 13 insertions, 10 deletions

diff --git a/docs/about/acknowledgements.rst b/docs/about/acknowledgements.rst
index a9f64511..dfc66c8f 100644
--- a/docs/about/acknowledgements.rst
+++ b/docs/about/acknowledgements.rst
@@ -6,7 +6,8 @@ Contributor Acknowledgements
    specific contributors referred to in "Arm Limited and Contributors" copyright
    notices. As contributors are now encouraged to put their name or company name
    directly into the copyright notices, this file is not relevant for new
-   contributions.
+   contributions. See the :ref:`License` document for the correct template to
+   use for new contributions.
 
 - Linaro Limited
 - Marvell International Ltd.
diff --git a/docs/about/features.rst b/docs/about/features.rst
index 9df28946..3441c5eb 100644
--- a/docs/about/features.rst
+++ b/docs/about/features.rst
@@ -3,7 +3,7 @@ Feature Overview
 
 This page provides an overview of the current |TF-A| feature set. For a full
 description of these features and their implementation details, please see
-:ref:`Firmware Design` and supporting documentation.
+the documents that are part of the *Components* and *System Design* chapters.
 
 The :ref:`Change Log & Release Notes` provides details of changes made since the
 last release.
@@ -34,7 +34,7 @@ Current features
    is also suitable for integration with other AArch32 EL3 Runtime Software,
    for example an AArch32 Secure OS.
 
--  A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate |PSCI| library
+-  A minimal AArch32 Secure Payload (*SP_MIN*) to demonstrate |PSCI| library
    integration with AArch32 EL3 Runtime Software.
 
 -  Secure Monitor library code such as world switching, EL1 context management
@@ -106,8 +106,8 @@ Still to come
 
 -  Refinements to Position Independent Executable (PIE) support.
 
--  Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT
-   specifications continue to evolve.
+-  Continued support for the draft SPCI specification, to enable the use of
+   secure partition management in the secure world.
 
 -  Documentation enhancements.
 
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 86e445a7..68f84ea5 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -19,8 +19,8 @@ Main maintainers
 :G: `AlexeiFedorov`_
 :M: Paul Beesley <paul.beesley@arm.com>
 :G: `pbeesley-arm`_
-:M: John Tsichritzis <john.tsichritzis@arm.com>
-:G: `jts-arm`_
+:M: György Szing <gyorgy.szing@arm.com>
+:G: `gyuri-szing`_
 
 Allwinner ARMv8 platform port
 -----------------------------
@@ -287,10 +287,10 @@ Xilinx platform port
 .. _etienne-lms: https://github.com/etienne-lms
 .. _glneo: https://github.com/glneo
 .. _grandpaul: https://github.com/grandpaul
+.. _gyuri-szing: https://github.com/gyuri-szing
 .. _hzhuang1: https://github.com/hzhuang1
 .. _JackyBai: https://github.com/JackyBai
 .. _jenswi-linaro: https://github.com/jenswi-linaro
-.. _jts-arm: https://github.com/jts-arm
 .. _jwerner-chromium: https://github.com/jwerner-chromium
 .. _kostapr: https://github.com/kostapr
 .. _ldts: https://github.com/ldts
diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst
index 3dd23e5b..9876531a 100644
--- a/docs/getting_started/user-guide.rst
+++ b/docs/getting_started/user-guide.rst
@@ -1764,6 +1764,7 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores
 -  ``FVP_Base_Cortex-A76AEx8``
 -  ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
 -  ``FVP_Base_Neoverse-N1x4``
+-  ``FVP_Base_Zeusx4``
 -  ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
 -  ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
 -  ``FVP_RD_E1Edge`` (Version 11.3 build 42)
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 57296351..5495280a 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -86,6 +86,7 @@ CPU cores (64-bit host machine only).
 -  ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
 -  ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
 -  ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
+-  ``FVP_Base_Zeusx4``
 -  ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
 -  ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
 -  ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
@@ -103,8 +104,8 @@ CPU cores (64-bit host machine only).
 .. note::
    The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities.
 
-The *Foundation* FVP can be downloaded free of charge. The *Base* FVPs can be
-licensed from Arm. See the `Arm FVP website`_.
+The *Foundation* and *Base* FVPs can be downloaded free of charge. See the
+`Arm FVP website`_.
 
 All the above platforms have been tested with `Linaro Release 19.06`_.