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| author | lauwal01 <lauren.wehrmeister@arm.com> | 2019-06-24 11:38:53 -0500 |
|---|---|---|
| committer | lauwal01 <lauren.wehrmeister@arm.com> | 2019-07-02 09:16:10 -0500 |
| commit | 9eceb020d79614cf41d64f6eae4086f3b5390203 (patch) | |
| tree | c0d19c0446266b7ac3d4a6fb5df0132140e0c334 /docs | |
| parent | ef5fa7d47741d008f8786f971fc138e6331fb46d (diff) | |
Workaround for Neoverse N1 erratum 1220197
Neoverse N1 erratum 1220197 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUECTLR_EL1 system register, which disables write streaming to the L2.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index ef24f2e3..ee8da176 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -240,6 +240,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. +- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r2p0 of the CPU. + - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. |