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authorJustin Chadwell <justin.chadwell@arm.com>2019-07-18 16:16:32 +0100
committerJustin Chadwell <justin.chadwell@arm.com>2019-09-09 16:23:41 +0100
commit88d493fb1b0a780809aea491fc30a145af92930b (patch)
tree0858a166b5cdc848a5a2f6efb41d4622ce4db815 /docs
parent9dd94382bd23db0fa201b254dc3f1bebdfd627c2 (diff)
Add documentation for CTX_INCLUDE_MTE_REGS
A new build flag, CTX_INCLUDE_MTE_REGS, has been added; this patch adds documentation for it in the User Guide along with instructions of what different values mean. Change-Id: I430a9c6ced06b1b6be317edbeff4f5530e30f63a Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Diffstat (limited to 'docs')
-rw-r--r--docs/design/firmware-design.rst11
-rw-r--r--docs/getting_started/user-guide.rst8
2 files changed, 18 insertions, 1 deletions
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index 00e199a2..dc082082 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -2581,7 +2581,16 @@ Armv8.5-A
~~~~~~~~~
- Branch Target Identification feature is selected by ``BRANCH_PROTECTION``
- option set to 1. This option defaults to 0 and this is an experimental feature.
+ option set to 1. This option defaults to 0 and this is an experimental
+ feature.
+
+- Memory Tagging Extension feature is unconditionally enabled for both worlds
+ (at EL0 and S-EL0) if it is only supported at EL0. If instead it is
+ implemented at all ELs, it is unconditionally enabled for only the normal
+ world. To enable it for the secure world as well, the build option
+ ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement
+ MTE support at all, it is always disabled, no matter what build options
+ are used.
Armv7-A
~~~~~~~
diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst
index b447f149..855a7971 100644
--- a/docs/getting_started/user-guide.rst
+++ b/docs/getting_started/user-guide.rst
@@ -383,6 +383,13 @@ Common build options
registers to be included when saving and restoring the CPU context. Default
is 0.
+- ``CTX_INCLUDE_MTE_REGS``: Enables register saving/reloading support for
+ ARMv8.5 Memory Tagging Extension. A value of 0 will disable
+ saving/reloading and restrict the use of MTE to the normal world if the
+ CPU has support, while a value of 1 enables the saving/reloading, allowing
+ the use of MTE in both the secure and non-secure worlds. Default is 0
+ (disabled) and this feature is experimental.
+
- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
registers to be included when saving and restoring the CPU context as
@@ -798,6 +805,7 @@ Common build options
cluster platforms). If this option is enabled, then warm boot path
enables D-caches immediately after enabling MMU. This option defaults to 0.
+
Arm development platform specific build options
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^